100Gbps Ethernet PHY only testbench
Introduction
This design example allows you to simulate Altera 100Gbps Ethernet IP Core that does not include MAC so that you can get the better understanding how the control/status signals behave. Please note that this is not for Altera Low Latency 100Gbps Ethernet PHY IP Core.
System Requirements
Quartus Prime Software version 16.0.2 ModelSim-SE 10.4d
Download
E100g PHYonly.zip
Simulating the testbench
- Unzip the download file
- Open Modelsim-SE
- Change the directory to ./simulation/modelsim
- Type this command:
do run_1sttime.tcl
If you get error messages on Quartus install directory:
- Open ./simulation/modelsim/run_1sttime.tcl with a text editor
- Replace '$env(QUARTUS_ROOTDIR)' with your Quartus install directory path name. E.g. "c:/altera/16.0.2/quartus/"
Register Read/Write Operation
The minimum pulse width requirement for both status_read and status_write is one clk_status cycle. The read latency is supposed to be variable, thus you have to wait for status_readdata_valid to complete the read operation.
0/08/E100g_status_rw.PNG
MII TX Operation
The 100Gbps Ethernet PHY IP Core has DC-FIFO inside to compensate the clock frequency difference between the MII TX clock (clk_txmac, 315.0 MHz or higher frequnency) and the internal 312.5 MHz clock. To avoid FIFO overflow/underflow, tx_mii_valid must be deasserted for the same cycles as tx_mii_ready, and the tx_mii_valid deassertion shouldn't be later than a few clock cycles after tx_mii_ready deassertion since the FIFO depth is shallow. The TX PHY accepts START (data = 8'hFB, control = 1'b1) located only on mii_tx_data[7:0]/[71:64]/[135:128]/[199:192]/[263:256]. If the START is mapped to wrong byte positions, the TX PHY generates error codes (data = 8'hFE, control = 1'b1).
f/f4/E100g_mii_tx.PNG
MII RX Operation
The RX also has DC-FIFO to compensate the clock frequency difference between the internal 312.5 MHz and the MII RX clock (rx_macclk, 315 MHz or higher frequency). Your logic needs to expect the rx_mii_valid can be deasserted during frame receptions.
5/50/E100g_mii_rx.PNG
