AXI Support
The Quartus® II software version 11.1 introduced initial support for industry-standard AMBA® AXITM interfaces from ARM in the Qsys system integration tool.
Qsys components can now include AXI master and slave interfaces, and these interfaces can connect with other AXI interfaces or with Avalon® masters and slaves.
Because the support for AXI interfaces in version 11.1 was considered beta, AXI support is not included in Altera’s published documentation. This page lists more details about the AXI support in version 11.1.
Beginning with the Quartus II software versions 12.0, AXI interface support is described in the Quartus II Handbook. Refer to the Qsys Interconnect chapter for details about AMBA AXI support.
In version 11.1, Qsys supports only simple single-cycle transactions. This version does not support burst transactions or non-full size transactions (AXI SIZE field).
The interconnect processes all transactions in-order. Out-of-order responses may be supported in a future version.
There are no AXI bus functional models (BFMs) provided in this version.
The following list details support and limitations for AXI3 signals:
- Clocks and resets: Supported
- Write and read address channels: All signals supported
- Address limited to 32 bits
- ID width limited to 18 bits
- Write data, write response and read response channels: All signals supported
- Data widths limited to maximum of 256 bits
- Low power channel: No support for the low power extensions
The following additional features are not currently supported:
- Cache: AWCACHE and ARCACHE
- Protection unit: AWPROT / ARPROT signals
- Atomic accesses: Exclusive access support
- Response signaling
- Write data interleaving
- Narrow data buses
- Unaligned transfers
- Width adaptation
