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Altera 1588 System Level Solution

Altera 1588 System Level Solution



Last Major Update 

February 14, 2015

 

Objective

The objective of the wiki page is to provide an overview to user about Altera 1588 solution at a system level and positioning of Altera’s Ethernet MAC and PCS+PMA with 1588 hardware IP capable of time-stamping PTP packets with very high accuracy down to a few nanoseconds.


Introduction

IEEE 1588 v2 (IEEE Standards Association, 2008) is standard that defines a precision timing protocol (PTP) used in packet networking to precisely synchronize the real time-of-day (ToD) clocks and frequency sources in a distributed system to a master ToD clock, which in turn is synchronized to a global clock source. With the advent of 1588 v2, it makes synchronization to the tune of nanoseconds within packet networks, enabling low-cost phase and frequency synchronization in applications such as wireless, mobile backhaul, wireline and industrial instrumentation potentially replacing the costlier TDM networks used for similar purposes. The 10M-10G Ethernet low-latency MAC and PCS+PMA (PHY) 1588 solution from Altera supports a static error of +/- 3ns across the throughputs of 10Gbps, 1Gbps & 100Mbps with the random error of +/- 1ns, +/- 2ns, and +/- 5ns from the PHY for the throughputs of 10Gbps, 1Gbps & 100Mbps respectively. 

For more details of Altera 1588 information, please refer to :Altera_1588_solution


The document attached covers:


■ System Level Block diagram involving Altera Ethernet +1588 IP ; TOD, MAC+PHY 1588 IP ,Packet Parser, CPU and FIFO/CAM. 

■ 1-step mechanism and 2-step mechanism 

■ 1588 Synchronization process between master and Slave clocks 

■ PTP clocks : Ordinary Clock, Transparent Clock and Boundary Clock 

■ 1588 master/slave functional flow of Altera 1588 hardware IP in different PTP clock

Version history
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Last update:
‎06-21-2019 06:38 PM
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