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Arria 10 Transceiver PHY Pin Planning

Arria 10 Transceiver PHY Pin Planning


Arria 10 Pin Planning Design (Unofficial)

How to use Arria 10 Pin Planning tool to quickly develop and validate your transceiver based design.

Arria 10 Pin Planning Documentation Example 1

The document link below describes how a user can quickly develop an A10 pinout using some of the common IP’s that are used for Transceiver based systems. This includes the fundamental building block of the Native PHY, and other IP’s such as Hard PCIe (Gen 2 and Gen3) and the TSE(Triple Speed Ethernet) IP.

File:Using the A10 Pin Planner design v001.zip

Arria 10 Pin Planning Design Example 1

This design example shows implementation of Native PHY, and other IP’s such as Hard PCIe (Gen 2 and Gen3) and the TSE(Triple Speed Ethernet) IP.

Arria 10 Pin Planning Design File 1

File:FPGA TOP A10 Pin Planner Design.qar 

Arria 10 Pin Planning Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
DeviceArria 10
Quartus versionQuartusII v14.0a10s
Modelsim versionModelsim SE v10.4d
DatarateVarious
Data patternVarious
Number of channelsVarious
IP usedNative PHY IP,ATX PLL IP, fPLL IP,Transceiver PHY reset controller


Arria 10 Pin Planning Documentation Example 2

The document link below describes how a user can quickly develop an A10 pinout using some of the common IP’s that are used for Transceiver based systems. This includes the fundamental building block of the Native PHY, and other IP’s such as Hard PCIe (Gen 2 and Gen3), TSE(Triple Speed Ethernet),XAUI, 10G Base-KR, Seriallite III, LL 10G/40G, Interlaken, JESD204B IP.

File:Using the A10 Pin Planner design v002.zip

Arria 10 Pin Planning Design Example 2

This design example shows implementation of Native PHY, and other IP’s such as Hard PCIe (Gen 2 and Gen3) TSE(Triple Speed Ethernet),XAUI, 10G Base-KR, Seriallite III, LL 10G/40G, Interlaken, JESD204B IP.

Arria 10 Pin Planning Design File 2

A10 Pin Planner Design 

Arria 10 Pin Planning Design Specifications

The table below lists the specifications for this design:

AttributeSpecification
DeviceArria 10
Quartus versionQuartusII v14.0a10s
Modelsim versionModelsim SE v10.4d
DatarateVarious
Data patternVarious
Number of channelsVarious
IP usedNative PHY IP,ATX PLL IP, fPLL IP, Transceiver PHY reset controller




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Version history
Revision #:
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Last update:
‎06-21-2019 08:46 PM
Updated by:
 
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