Arria10 Transceiver PHY Basic Design Examples
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Arria 10 Native PHY dynamic reconfiguration with embedded streamer and standard PCS design example
Overview
This basic design example with Modelsim simulation demonstrates the implementing of Arria 10 Native PHY dynamic reconfiguration with embedded streamer and standard PCS . The purpose of this design example is to assist users to have quick start with the Arria 10 transceiver dynamic reconfiguration with embedded streamer and multiple profile. The design consist of two transceiver channels with fixed data pattern. The example will demonstrate dynamic reconfiguration of one channel a time as well as broadcast mode where two channels are reconfigured at the same time. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The Qsys source files of the IPs used for HDL generation is in the source folder of the zip. Note that you should create your reconfiguration controller and AVMM read/write controller as these controls are done in test bench in the example.
To run the simulation, do the following:
1. Unzip the files
2. Change the Modelsim directory to the unzipped folder
3. Type "source simulation_setup.tcl"
4. Type "ld" to compile
5. Type "simulate" to start simulation
Design File
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Arria 10 GX |
| Quartus version | Quartus Prime v15.1 |
| Modelsim version | ModelSim ALTERA STARTER EDITION 10.4b |
| Datarate | 2Gbps and 1Gbps |
| Data pattern | Fixed |
| Number of channels | 2 |
| IP used | Native PHY IP, ATX PLL, Transceiver PHY Reset Controller |
Arria 10 Native PHY dynamic reconfiguration with embedded streamer and enhanced PCS design example
Overview
This basic design example with Modelsim simulation demonstrates the implementing of Arria 10 Native PHY dynamic reconfiguration with embedded streamer and enhanced PCS . The purpose of this design example is to assist users to have quick start with the Arria 10 transceiver dynamic reconfiguration with embedded streamer and multiple profiles. The design consist of two transceiver channels with fixed data pattern. The example will demonstrate dynamic reconfiguration of one channel a time as well as broadcast mode where two channels are reconfigured at the same time. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The Qsys source files of the IPs used for HDL generation is in the source folder of the zip. Note that you should create your reconfiguration controller and AVMM read/write controller as these controls are done in test bench in the example.
To run the simulation, do the following:
1. Unzip the files
2. Change the Modelsim directory to the unzipped folder
3. Type "source simulation_setup.tcl"
4. Type "ld" to compile
5. Type "simulate" to start simulation
Design File
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Arria 10 GX |
| Quartus version | Quartus Prime v15.1 FAE Beta b164 |
| Modelsim version | ModelSim ALTERA STARTER EDITION 10.4b |
| Datarate | 5Gbps and 10Gbps |
| Data pattern | Fixed |
| Number of channels | 2 |
| IP used | Native PHY IP, ATX PLL, Transceiver PHY Reset Controller |
Arria 10 Native PHY dynamic reconfiguration with embedded streamer, standard PCS and TX PLL switching design example
Overview
This basic design example with Modelsim simulation demonstrates the implementing of Arria 10 Native PHY dynamic reconfiguration with embedded streamer, standard PCS and TX PLL switching. The two TX PLLs are used to support two different data rates which could not be achieved with TX local divider. The purpose of this design example is to assist users to have quick start with the Arria 10 transceiver dynamic reconfiguration with embedded streamer and multiple profiles. The design consist of two transceiver channels with fixed data pattern. This design will showing data rate switching between 1G and 2G with TX local divider fixed at 1 just as example only. The example will demonstrate dynamic reconfiguration of one channel a time as well as broadcast mode where two channels are reconfigured at the same time. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The Qsys source files of the IPs used for HDL generation is in the source folder of the zip. Note that you should create your reconfiguration controller and AVMM read/write controller as these controls are done in test bench in the example. The register value to write for TX PLL switching here is obtained manually through simulation. You should create your own mechanism to perform on-the-fly read-modify-write for TX PLL switching.
To run the simulation, do the following:
1. Unzip the files
2. Change the Modelsim directory to the unzipped folder
3. Type "source simulation_setup.tcl"
4. Type "ld" to compile
5. Type "simulate" to start simulation
Design File
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Arria 10 GX |
| Quartus version | Quartus Prime v15.1 |
| Modelsim version | ModelSim ALTERA STARTER EDITION 10.4b |
| Datarate | 1Gbps and 2Gbps |
| Data pattern | Fixed |
| Number of channels | 2 |
| IP used | Native PHY IP, ATX PLL, Transceiver PHY Reset Controller |
Arria 10 Native PHY dynamic reconfiguration with embedded streamer, standard/enhanced PCS and TX PLL switching design example
Overview
This basic design example with Modelsim simulation demonstrates the implementing of Arria 10 Native PHY dynamic reconfiguration with embedded streamer, standard and enhanced PCS switching as well as TX PLL switching. The two TX PLLs are used to support two different data rates which could not be achieved with TX local divider. The purpose of this design example is to assist users to have quick start with the Arria 10 transceiver dynamic reconfiguration with embedded streamer and multiple profiles. The design consist of two transceiver channels with fixed data pattern. The example will demonstrate dynamic reconfiguration of one channel a time as well as broadcast mode where two channels are reconfigured at the same time. The design will reconfigure the channels between standard and enhanced PCS. The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The Qsys source files of the IPs used for HDL generation is in the source folder of the zip. Note that you should create your reconfiguration controller and AVMM read/write controller as these controls are done in test bench in the example. The register value to write for TX PLL switching here is obtained manually through simulation. You should create your own mechanism to perform on-the-fly read-modify-write for TX PLL switching.
To run the simulation, do the following:
1. Unzip the files
2. Change the Modelsim directory to the unzipped folder
3. Type "source simulation_setup.tcl"
4. Type "ld" to compile
5. Type "simulate" to start simulation
Design File
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Arria 10 GX |
| Quartus version | Quartus Prime v15.1 FAE Beta b164 |
| Modelsim version | ModelSim ALTERA STARTER EDITION 10.4b |
| Datarate | 2Gbps and 5Gbps |
| Data pattern | Fixed |
| Number of channels | 2 |
| IP used | Native PHY IP, ATX PLL, Transceiver PHY Reset Controller |
Arria 10 Native PHY with ATX PLL location manually constrained design example
Overview
This basic design example with demonstrates how to manually constrain the Arria 10 ATX PLL location using Assignment Editor. In Arria 10 devices, ATX PLL spacing is required when two ATX PLLs operate at the same VCO frequency or within 100MHz difference. This is to avoid jitter performance issue with the ATX PLLs. In this design, the ATX PLL location has been pre-assigned. You can refer to the assignment example in the Assignment Editor.
To manually constrain the ATX PLL location in the design, do the following steps:
1. Extract the project QAR
2. Run Analysis & Synthesis compilation
3. Open up RTL Viewer
4. Look for twentynm_atx_pll_inst (the lowest level node of ATX PLL in RTL viewer)
5. Right click on the twentynm_atx_pll_inst and Locate Node in Assignment Editor
6. Populate the twentynm_atx_pll_inst into the "To" column of Assignment Editor
7. Select Assignment Name = Location
8. At the "Value" column, look for Element = ATX PLL and select the target ATX PLL location
9. Save and recompile the design
10. Check the Fitter report -> GXB Reports -> Transmitter PLL for the location placed
Design File
Arria 10 Native PHY with ATX PLL location manually constrained design example QII v15.1 (QAR)
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Arria 10 GX |
| Quartus version | QuartusII v15.1 |
| Datarate | 1Gbps |
| Number of channels | 1 |
| IP used | Native PHY IP, ATX PLL, Transceiver PHY Reset Controller |
Arria 10 Native PHY PCS direct with rx_pma_clkslip design example
Overview
This basic design example with Modelsim simulation demonstrates the implementing of Arria 10 Native PHY in PCS direct mode with rx_pma_clkslip. The purpose of this design example is to assist users to have quick start with the Arria 10 transceiver in PCS direct mode. The design consist of one transceiver channel configured in PCS direct mode with both fixed and incremental data patterns. The TX data is loopbacked to RX and rx_pma_clkslip is used to achieve the correct word alignment boundary. Fixed data is sent initially and after correct word boundary is found, incremental data is sent. The Qsys source files of the IPs used for HDL generation is in the source folder of the zip. Note that you should create your own bit slip mechanism, pattern generator and checker because these are done in test bench in the example. In addition, please note that a rising edge on the rx_pma_clkslip signal causes the RX serializer to slip the serial data by 2 UI. There might be cases where you are not able to find the right word boundary. In this case, you might need to add your own word alignment logic or check the binary bits to see if correct data received.
To run the simulation, do the following:
1. Unzip the files
2. Change the Modelsim directory to the unzipped folder
3. Type "source simulation_setup.tcl"
4. Type "ld" to compile
5. Type "simulate" to start simulation
Design File
Arria 10 Native PHY PCS direct with rx_pma_clkslip design example Q16.0 (ZIP)
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Arria 10 GX |
| Quartus version | Quartus Prime 16.0 |
| Modelsim version | ModelSim ALTERA EDITION 10.4d |
| Datarate | 10.3125Gbps |
| Data pattern | Fixed and incremental |
| Number of channels | 1 |
| IP used | Native PHY IP, ATX PLL, Transceiver PHY Reset Controller |
Arria 10 Native PHY with serial loopback design example
Overview
This basic design example demonstrates one transceiver channel link loopback test with internal serial loopback in Arria 10 device. By having the serial loopback in place, it allows you to focus on the transceiver blocks debugging and get away from external factors ie signal integrity. In this design, In-System Source and Probe (ISSP) is used to control the reset, RX bistlip and serial loopback of the Native PHY. ISSP allows real time interface with the Arria 10 device through JTAG. This design has been tested with Arria 10 GX Transceiver Signal Integrity Development Kit.
After downloading the SOF file, you will need to launch the In-System Source and Probe Editor at the Quartus Prime -> Tools menu. Write a value of '1' to the source[2] in the ISSP Editor to enable the internal serial loopback. In this design, fixed data pattern 0xBC is sent from TX to RX. You can open up the SignalTap stp1.stp file to monitor the RX parallel data. You may apply rx_bitslip by controlling source[1] in ISSP Editor to get to the right word boundary.
Design File
Arria 10 Native PHY with serial loopback design example Q15.1 (QAR)
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Arria 10 GX |
| Quartus version | Quartus Prime 15.1.2 |
| Datarate | 1.25Gbps |
| Data pattern | Fixed |
| Number of channels | 1 |
| IP used | Native PHY IP, ATX PLL, Transceiver PHY Reset Controller |
Arria 10 Native PHY simplex transmitters and receivers placed in the same physical transceiver channel location design examples
Overview
These basic design examples demonstrate how to place the Arria 10 Native PHY simplex transmitters and receivers in the same physical transceiver channel location by sharing the reconfiguration interfaces. By default, when you enable the dynamic reconfiguration for simple transmitters and receivers, Quartus will not allow them to be placed into the same physical channel location. You can workaround this by using XCVR_RECONFIG_GROUP assignment to share the reconfiguration interfaces. In this design, the XCVR_RECONFIG_GROUP assignment have been pre-assigned. You can refer to the assignment example in the Assignment Editor for further details.
Design File
Arria 10 Native PHY one channel simplex transmitter and receiver merged design example Qv15.1 (QAR)
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Arria 10 GX |
| Quartus version | Quartus Prime v15.1.2 |
| Datarate | 5Gbps |
| Number of channels | 1, 2 |
| IP used | Native PHY IP, ATX PLL, Transceiver PHY Reset Controller |
Arria 10 Native PHY with Transceiver Toolkit design example
Overview
This basic design example demonstrates one transceiver channel link which can work with the XCVR toolkit in Arria 10 device. With the Transceiver toolkit, it allows you to perform auto sweep to find the optimal analog settings for a specific board setup. You can then port the optimal settings found back to your own design and further fine tune from there. This design has been tested with Arria 10 GX Transceiver Signal Integrity Development Kit.
After downloading the SOF file, you may launch the Transceiver Toolkit at the Quartus Prime -> Tools -> System Debugging Tools -> Transceiver Toolkit. Then load the design into Transceiver Toolkit and the transceiver channel should be auto-populated in the Transceiver Toolkit.
Design File
Arria 10 Native PHY with Transceiver Toolkit design example Q15.1 (QAR)
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Arria 10 GX |
| Quartus version | Quartus Prime 15.1.2 |
| Datarate | 1.25Gbps |
| Data pattern | Fixed |
| Number of channels | 1 |
| IP used | Native PHY IP, ATX PLL, Transceiver PHY Reset Controller |
Arria 10 Native PHY design example showing converged DFE tap values reading steps
Overview
This basic design example demonstrates how to read the converged DFE tap values using system console in Arria 10 Native PHY. In adaptive mode, the DFE tap values are controlled by the Adaptive Parametric Tuning Engine and will converge to specific values. This design example shows the reading of DFE tap 1 value. Similar method is applicable to other tap with different register address. You may refer to the detailed steps in the read_adapt_dfe.tcl.
To read the converged DFE tap 1 value, do the following steps:
1. Extract the project QAR
2. Compile the design and program the SOF file into the device
3. Transceiver Toolkit and establish connection to the device
4. Enable the serial loopback
5. Start sending data from TX to RX
6. After the RX is lock-to-data, click on the Start Adaptation in XCVR Toolkit
7. At the TCL console, type "source read_adapt_dfe.tcl "
8. Type "read_adapt_dfe_1” to read the converged DFE tap1 through AVMM interface
Design File
Arria 10 Native PHY design example showing converged DFE tap values reading steps Q16.0 (QAR)
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Arria 10 GX |
| Quartus version | Quartus Prime v16.0 |
| Development kit | Arria 10 GX Signal Integrity devkit |
| Number of channels | 1 |
| IP used | Native PHY IP, ATX PLL, Transceiver PHY Reset Controller |
Arria 10 GX Dynamic Serial, Pre and Post CDR Loopback Modes Design Example
Overview
This design example is to demonstrates dynamic enabling and disabling of different loopback modes supported in the Arria 10 transceiver using direct reconfiguration flow. The loopback modes supported include serial loopback, reverse serial loopback pre-CDR and reverse serial loopback post-CDR. The simulation example will use a link test between two transceiver channels to demonstrates the different behaviours at the RX parallel data outputs with different loopback modes.
To run the simulation, do the following:
1. Unzip the files
2. Change the Modelsim directory to the unzipped folder
3. Type "source simulation_setup_top.tcl"
4. Type "ld" to compile
5. Type "simulate" to start simulation
Design File
Arria 10 GX Dynamic Serial, Pre and Post CDR Loopback Modes Design Example Q16.0 (ZIP)
Design Specifications
The table below lists the specifications for this design:
| Attribute | Specification |
| Device | Arria 10 GX |
| Quartus version | Quartus Prime 16.0 |
| Modelsim version | ModelSim ALTERA EDITION 10.4d |
| Datarate | 5Gbps |
| Data pattern | Fixed |
| Number of channels | 2 |
| IP used | Native PHY IP, fPLL, Transceiver PHY Reset Controller |
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