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Avalon-MM to Software Programmable SPI Master

Avalon-MM to Software Programmable SPI Master

(Redirected from Avalon-MM to Configurable SPI Master)



Design Files File:Custom spi master.zip

Software Programmable SPI Master Core

This design implements a SPI Master which can be configured on-the-fly. It supports the following options, all dynamic through register accesses:


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  • Configurable transaction length, up to 128 bits
  • Configurable SPI clock speed
  • Configurable MSB or LSB transfer and positive or negative clock alignment
  • Up to 32 CS outputs
  • Dynamic delay on TX and RX paths relative to SPI clock edge
  • Design fully synchronous to system clock, input data latched through metastability registers

To initiate a transaction:

  1. Write the data into the dataout3, dataout2, dataout1 and dataout0 registers which contain the entire 128 bit word from MSB to LSB.
  2. Write to the activity define register and set the transaction type and length, write the go busy bit to start the transaction.
  3. The read data is available once the go busy bit deasserts in the datain3, datain2, datain1 and datain0 registers respectively.

To simplify the logic structure the design takes advantage of internal RAM blocks which allows a 16 to 1 conversion. Once go busy bit is assert the state machine will first write the data into the RAM and then proceed with the transaction depending on the settings of the activity_define_register.

Design Utilization

This design uses ~313 ALMs and has a fmax of 471 MHz in a Stratix V C2 device.


Register Interface

The register interface is setup so that parameters can be used to change the address locations. Much of that functionality has not been tested.

clock_div_register – 0x0

[31:0] – 32 bits Provides the SPI serial clock and is derived from the main clock input to the module. It is governed by the following formula: clock frequency = clock/((clock_div_register + 1) * 2)

dataout0_register – 0x1

[31:0] – 32 bits Contains the low word of the SPI data register and contains data that will be written from the SPI master. The output data stream is up to 128 bits and can either be shifted from the MSB or LSB. The LSB location can be arbitrarily defined via the transaction length and lsb first bits in the activity_define_register. The data is concatenated as { dataout3, dataout2, dataout1, dataout0 }

dataout1_register – 0x2

[31:0] – 32 bits Contains the second to lowest word of the SPI data register and contains data that will be written from the SPI master. The output data stream is up to 128 bits and can either be shifted from the MSB or LSB. The LSB location can be arbitrarily defined via the transaction length and lsb first bits in the activity_define_register. The data is concatenated as { dataout3, dataout2, dataout1, dataout0 }

dataout2_register – 0x3

[31:0] – 32 bits Contains the second to highest word of the SPI data register and contains data that will be written from the SPI master. The output data stream is up to 128 bits and can either be shifted from the MSB or LSB. The LSB location can be arbitrarily defined via the transaction length and lsb first bits in the activity_define_register. The data is concatenated as { dataout3, dataout2, dataout1, dataout0 }

dataout3_register – 0x4

[31:0] – 32 bits Contains the high word of the SPI data register and contains data that will be written from the SPI master. The output data stream is up to 128 bits and can either be shifted from the MSB or LSB. The LSB location can be arbitrarily defined via the transaction length and lsb first bits in the activity_define_register. The data is concatenated as { dataout3, dataout2, dataout1, dataout0 }

datain0_register – 0x5

[31:0] – 32 bits Contains the low word of the SPI data input register. While CS is high data is sampled continually as defined by the activity_define_register settings. The maximum data capture with is 128 bits. After CS deasserts you can read this data from 4, 32 bit registers. The data is split from the main 128 bit sample register . This register contains bits [31:0].

datain1_register – 0x6

[31:0] – 32 bits Contains the low word of the SPI data input register. While CS is high data is sampled continually as defined by the activity_define_register settings. The maximum data capture with is 128 bits. After CS deasserts you can read this data from 4, 32 bit registers. The data is split from the main 128 bit sample register . This register contains bits [63:32].

datain2_register – 0x7

[31:0] – 32 bits Contains the low word of the SPI data input register. While CS is high data is sampled continually as defined by the activity_define_register settings. The maximum data capture with is 128 bits. After CS deasserts you can read this data from 4, 32 bit registers. The data is split from the main 128 bit sample register . This register contains bits [95:64].

datain3_register – 0x8

[31:0] – 32 bits Contains the low word of the SPI data input register. While CS is high data is sampled continually as defined by the activity_define_register settings. The maximum data capture with is 128 bits. After CS deasserts you can read this data from 4, 32 bit registers. The data is split from the main 128 bit sample register . This register contains bits [128:96].

chip_select_register – 0xB

[31:0] – 32 bits Register which allows you to drive up to 32 chip select signals simultaneously. The spi_state_machine block will drive the chip select for the appropriate transaction width and this register will allows you to fan that single chip select to multiple or different single chip select outputs.

activity_define_register – 0x9

[31:0] – 32 bits Main control register which defines how the SPI interface will behave. Details on the bit mapping within the register are in the table below.

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transaction length – these register bits define the length of the SPI data transfer in clocks or bits. Maximum length in 128.

go busy bit – after setting up the transaction parameters this bit needs to be set to 1. You can poll this bit to determine if the SPI Master is active. Once the transaction is complete this bit will return to 0.

toggle level rx – setting this to a 1 means a positive clock edge capture, 0 means a negative clock edge capture

toggle level tx – setting this to a 1 means a tx transfer on the negative clock edge (centered around the positive edge), 0 means a transfer on the positive edge (centered around the negative clock).

lsb first – settings this to 1 means the LSB will be the first data bit sent; 0 means the MSB (governed by the transaction length) will be sent first.

Interrupt enable (NOT IMPLEMENTED) – setting this to a 1 will generate a interrupt when the go busy bit deasserts

auto cs – ability to keep the chip select active all of the time

toggle delay low tx, toggle delay high tx – these bits give the option to delay the data transition on the TX side for up to 4 system clocks (00 = 1 clock, 01 = 2 clocks, 10 = 3 clocks 11 = 4 clocks) from the edge selected by the toggle level tx setting.

toggle delay low rx, toggle delay high rx – these bits give the option to delay the data capture on the RX side for up to 4 system clocks (00 = 1 clock, 01 = 2 clocks, 10 = 3 clocks 11 = 4 clocks) from the edge selected by the toggle level rx setting. toggle delay low rx – setting this bit high enables the delay detailed in the toggle delay low rx, toggle delay high rx settings

toggle delay low tx – setting this bit high enables the delay detailed in the toggle delay low tx, toggle delay high tx settings

chip_select_register – 0xB

[31:0] – 32 bits Allows the user to control the CS signal that is active, more than one CS may be active at one time. Please note there is only one SDI input to the design so this multi-drive functionality is not useful for read back only for driving multiple endpoints simultaneously.

Simulation

Included in this design is a simulation testbench, tb_custom_spi_master.v. A number of different transaction types are modeled in the current simulation and the end user can add more. For the purposes of test the TX is looped back to the RX although a SPI slave could be attached instead. The testbench contains tasks, avalon_write and avalon_read, which can be used to communicate with the Avalon-MM interface side of the core. Here is an example transaction with a gap to allow the transaction to complete.


To run the simulation you can use the simulation script sim.do in QuestaSim or ModelSim. This illustrates all of the files required to simulate this design including Altera models. If the paths are different in your system you will need to modify this script to account for those changes. Here is the full simulation waveform and a zoom of a transaction.

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