This tool is targeted to be used in Microsoft Excel 2010. You may face compatibility issues with earlier versions of Excel.
PCB traces can have skews between them which can cause timing margins to be reduced. Further, margin reduction can occur due to skews between different ranks in multi-rank topologies. With the increase in operating frequencies for memory interfaces, it has become increasingly important to enter accurate Board Skew Parameters for the External Memory Interfaces IP during the IP Catalog flow. This tool will enable you to calculate these board skew parameters faster and easily. You can calculate these parameters by selecting your memory interface configuration and then entering in simulated trace delays for memory interface traces. For "How to Simulate", please refer to this Altera wiki(http://www.alterawiki.com/wiki/Arria_10_EMIF_Simulation_Guidance)
The tool workbook has been divided into 5 sheets:
This page acts as the 'Home' Page for the Tool
2. Interface IP:
Choose either the Arria 10 IP button for Arria 10 External Memory Interfaces IP or UniPHY IP button for UniPHY External Memory Interfaces IP depending on the interface you have chosen in the Altera IP Catalog.
3. Choose Protocol:
Choose the protocol you want to calculate board skew parameters for (should match the protocol chosen in the Altera IP Catalog
DDR3, DDR4, QDRII/II+/II+Xtreme, QDR4 ,RLDRAM3
DDR2, DDR3, LPDDR2, QDRII/II+/II+Xtreme, RLDRAM 2&3
Fig-1: Arria10 DRR4 EMIF Protocol BSPT IP Parameter pop-up Window.
Users will choose their configuration in the pop-up toolbox window
Enter in your simulated trace delays and package delays into tables
i. Blank spaces does not equal to 0.
ii. Please enter a value between the maximum and minimum table delays for all unused blank spaces. For Example. If there are 3 CK trace delay cells and you only want to use 2, choose one of the actual trace delay values from the two cells and copy it into the 3rd cell. The tool will use 0 as the minimum trace delay if left blank which will lead to wrong Board Skew Parameter calculations
iii. Enter delays inside the whitespaces only. If users modify any non-white areas, the tool may calculate inaccurate board skews
iv. Enter in package delays for traces you plan to deskew with board traces (The tool will calculate the total delay for you)
5. Skew Calculation:
This sheet holds the calculated skew which needs to be entered into External Memory Interface IP parameter's board skew tab. It is highly recommended to use these calculated delay for IP generation to get accurate timing closure.
For re-calculation, please restart the entire process by going back to first sheet(Introduction Sheet) using back button. Doing so will reset all global variable assignment to initial values and avoid any incorrect calculation which occurs due to the use of global variables with non-initial values.
Frequently asked questions (FAQ's):
Q. When should I use this tool?
Ans: This tool should be used during memory IP generation in IP Catalog to enter accurate Board Skew Parameter Values calculated from user's PCB delay. The tool calculates these Board Skew Parameters accurately, and displays it to you on the "Skew Calculations" Page. These parameters are entered under the Board Timing Tab > Board and Package Skews in the IP Catalog GUI.
Q. How accurate is this tool?
Ans: The tool calculates board skew parameters according to Altera recommended formula best suited for using our FPGA products.
Q. Where can I download this tool or check for newer versions?
Ans: The tool can be found under Board Skew Parameter Tool (XLS) on Altera's External Memory Interface Solutions Center:
Download using the link at the bottom of this wikipage
Please keep checking above link for newer versions or any updates made to the tool
Q. Why there is no support for LPDDR3 ?
Ans: For LPDDR3, you can use DDR3 calculation support, as the underlying skew calculation equations are the same.
Measuring Delay Values:
Please follow the Altera EMIF Handbook when measuring delays (Page 92)
Non-fly-by topology (Balanced Tree)
Non Supported topologies
For multiple DDR discrete components/devices
Fig-2: Arria10 DRR4 EMIF Protocol pop-up Window 'Memory Device Width' Option.
Not supported BSPT Component Memory format configuration
Current version of the BSPT will not support the following configuration with components
Selecting the option of clamshell or no clamshell during the IP configuration pop-up window in BSPT, will not have any impact. This selection was created specifically for No clamshell configuration.