CPRI IQ Mapper Reference Design 14.0

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CPRI IQ Mapper Reference Design 14.0

Last update on 21 July, 2016 

- IQ Mapper/DeMapper RTL Generator Tools updated to version 1.5 

- CPRI IP v6 Webcore updated to 15.1.313

Introduction

Altera CPRI IP v6.0 MegaCore allows connection to any user-defined air standard IQ mapping or custom IQ mapping block generated from Altera IQ Mapper/De-Mapper Code Generation Tools. This reference design demonstrates the use of Altera CRPI IP v6.0 MegaCore with the customized IQ mapping logic. This example will elaborate on the following: 

• How to create and customize your IQ mapping logic using Altera CPRI IQ Mapper and De-Mapper Code Generation Tools 
• Demonstration of integrated customized IQ mapper and de-mapper to Altera CPRI IP v6.0 MegaCore 
• A ready reference design with integrated IQ mapping logic from the generation tool 

Figure 1.0 Top-level view of IQ Mapper logic to CPRI IP Core Integration 

Functional Description

Overall

This reference design transmits and receives CPRI data on a master loopback setup in a simulation environment. It comes with a complete transceiver setup required components such as Transmitter PLL, reset controller, and reconfiguration controller. The design highlights the usage of the generated code of the IQ Mapper and IQ Demapper where additional custom logic is built to support it. 

The transmission starts with the separated raw I and Q data are send over to the IQ Mapper after interleaving. The IQ Mapper encodes the 3 AxC data into the available user data plane slots in Radioframe according to the selected line bit rate. These standard data will now be transported into the L1 Physical Layer, Altera CPRI IP v6.0 via the Direct IQ Tx Interface with indication from the frame counters values from AUX Tx interface. 

On the receiving side, the Direct IQ Rx Interface together with the AUX Rx Interface will return the loopback IQ data. The combined IQ data is now extracted by the core and be passed on to the IQ Demapper. The IQ data are then decoded into individual AxC channel and de-interleaved to I and Q data. 

Functional Blocks

Table 1.0 Modules in the reference design

Module Name	MegaCore/MegaFunction Component	Description
wrapper_top	Customized component	Top-level file for reference design
rec_master_v6	CPRI IP v6.0 MegaCore	CPRI IP in master mode
txpll	Stratix V Transmitter PLL	Used to generate high speed clock for transmitter
reset_tx_ctrl	Transceiver PHY Reset Controller	Reset controller for transmitter
reset_rx_ctrl	Transceiver PHY Reset Controller	Reset controller for the receiver
reconfig_ctrl	Transceiver Reconfiguration Controller	Reconfiguration controller for transceiver calibration (not active in this design)
iq_mapper	Customized IP Mapper block	IP Mapper (with 3 AxC) generated by Code Generation Tool
iq_demapper	Customized IP DeMapper block	IP DeMapper (with 3 AxC) generated by Code Generation Tool
map_mem_if	Customized IP Mapper top-level	IP Mapper wrapper with FIFO to clock cross to user clock (dsp_clk) domain, interleaves IQ data
demap_mem_if	Customized IP DeMapper top-level	IP DeMapper wrapper with FIFO to clock cross to user clock (dsp_clk) domain, de-interleave IQ data

Table 2.0 Clocks and reset in reference design

Clock Name	Description
tx_pll_refclk	This is the reference clock for the transmitter PLL. The reference clock frequency varies according to the different reference designs as below: 10.1376 Gbps – 253.44MHz 9.8304 Gbps – 245.76 MHz 6144.0 Gbps – 153.6 MHz
rx_cdr_refclk	This is the reference clock for the receiver CDR. The reference clock frequency varies according to the different reference designs as below: 10.1376 Gbps – 253.44MHz 9.8304 Gbps – 245.76 MHz 6144.0 Gbps – 153.6 MHz
reconfig_clk	Reconfiguration clock frequency used for Reconfiguration Controller, reset controllers and the CPRI IP core. The typical frequency is 100-150MHz but these reference designs use 100MHz.
ex_delay_clk	Extended Delay Measurement clock used for the CPRI IP core to measurement the soft FIFO delay. For accurate measurement, a specific frequency is used; please refer to Altera CPRI IP v6.0 User Guide for more information.
cpri_10g_coreclk	Optional 307.2MHz core clock for the CPRI IP. This clock must be present when the core is used in 10.1376Gbps; clock source must be from the master clock that generates the tx_pll_refclk.
cpri_clkout	Core clock for the CPRI IP as well as the customized IQ Mapping logic. The core clock rates follows the current line bit rate as follow: 10.1376 Gbps – 307.2MHz (this is sourced from cpri_10g_coreclk) 9.8304 Gbps – 245.76 MHz 6144.0 Gbps – 153.6 MHz
dsp_clk	User customized clock for the IQ Mapping logic. This is the sampling clock used for the AxC channel. In these examples, the sampling clock is fixed to 245.76MHz
reset_n	Global reset that reset the entire core. Reset to CPRI IP User Guide for more details.
reset_tx_n	Reset transmission part of the core. Reset to CPRI IP User Guide for more details.
reset_rx_n	Reset reception part of the core. Reset to CPRI IP User Guide for more details.
ex_delay_reset_n	Reset the extended delay measurement logic. Reset to CPRI IP User Guide for more details.
cpri_rst_n	Reset the IQ Mapper and DeMapper logic

Figure 2.0 Reference Design Functional blocks with Clocking Scheme

Altera CPRI IQ Mapper/De-Mapper Code Generation Tool

Obtaining the tool

This tool is part of the package of the reference design. You will need to run it on a machine that recognizes .xlsm file extension, no installation required. 

 Click here to download

Figure 2.0 Software snapshot of IQ Mapper Tool 

Specification

Table 3.0 Supported Features of Code Generation Tool

Supported Features	Description
Line bit rate	Option 1-8 (614.4 Mbps up to 10.1376 Gbps)
Mapping Method	Method 1 (IQ Sample Based)
IQ Sample Width	4-20 bit
Number of AxC	1-40
Output RTL format	Verilog
Simulation support	Yes

GUI Features

“Configuration -> Line Rate” drop-down menu 

Select the desired line bit rate option

“Configuration -> Symmetrical DL/UL” 

Select “YES” to enable de-mapper to automatically mirror the mapper mapping in the “Mapper” tab, no User Plane Data Area will need to be filled on the “DeMapper” tab. Select “No” to allow different mapping scheme on the demapper, “DeMapper” User Plane Data Area must be filled.

“User Plane Data Area” 

Mapping of IQ bit data could be performed at User Plane Data Area. The bit data for desired AxC channel (AXC0…AXC39) could be selected from the drop-down menu. (Hints: Repeating bit of same AxC could be copied and pasted; incrementing AxC could be dragged and etc)

“Prepare User Plane Data” 

Generate the allowable User Plane Data Area of mapping by user; it is restricted by Line Rate configuration (Note: Previous mapping of data will be deleted)

“Output Folder” 

Select the path/folder where the IQ Mapper and De-mapper related files will be generated and stored after the clicking the “Generate Code” button.

"Generate Code" 

Generate the related files for the IQ mapping and de-mapping selected to the output folder.

How-to-use

1. Setup the “Line Rate”, “Symmetrical DL/UL” and “Output folder” configuration.
2. Click on “Prepare User Plane Data”.
3. Start filling in the User Plane Data Area.
4. After the filling completed, click on “Generate Code”

Output Design

The generated RTL codes are in Verilog format and will be located at <Output Folder\designs\lib\iq_mapper.v and iq_demapper.v>

Running Simulation

Both the generated iq_mapper.v and iq_demapper.v modules have different simulation environment, so they should be run separately.

1. Start Modelsim simulator and locate the simulation script at <Output Folder>\msim\<iq_mapper or iq_demapper>\run\run.do
2. Use command “do run.do” and wait for simulation to complete

Documentation 

Please find the IQ Mapper/De-mapper Code Generator User Guide here. 

Inquiry / Obtaining the Reference Design 

This design is available from Altera Design Store. If you need further assistance, please contact your local Altera Sales .

Disclaimer

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