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Cyclone III - Nios II - Starter board

I'm putting this page together as I blunder about trying to get Nios II running on the Altera Cyclone III start kit. Hopefully it will be useful to others once it is complete.

Note: This page is for the Cyclone III starter board only. It doesn't include the Cyclone III Nios II daughter board which includes ethernet + display amongst other things (NEEK system).

The objective is to only use free software to get up and running (a Nios II license will be required to operate without the JTAG connection and / or to sell the design commercially)

Stage 1 - Dev Software

Download and install Quartus II Web Edition 7.2 including Service Pack 1 Download and install Mega core IP library 7.2 followed by the Service Pack 1 Download and install Nios II Embedded Design Suite 7.2 followed by the Service Pack 1 (this is what I have used running on Windows XP. Later versions may work. Update this wiki with what you find)

Install Cyclone III Starter Kit software. My version was 7.1.0

(the following assumes that all programs are installed in their default locations.)

Stage 2a - Simple Nios - Hardware

Just to show that we have everything working. We start with a simple Nios example.

Start up Quartus II. Open up the Cyclone III small Nios example project. File -> Open Project - C:/altera/Kits/CycloneIII_Starter_Kit-v7.1.0/Examples/CIII_NiosII_Small/CIII_NiosII_Small.qpf

(Plug in the Cyclone III startkit if you haven't already. Both power and USB lead is required)

Bring up the programmer in Quartus II. Tools -> Programmer

Use the Setup Hardware tab to select the USB Blaster if it is not already selected.

Hit Start to download the simple Nios design into the dev kit.

The Power and Conf_Done LEDs will be lit but everything else will be off. The Processor is now running on the board but it doesn't have any software to control it.

(More details on this Nios processor and how to generate it from scratch is available at http://www.altera.com/literature/tt/tt_nios2_hardware_tutorial.pdf.

Stage 2b - Simple Nios - Software

(I am not an expert on the Nios IDE so this might not be the simplest way of doing things but it works)

Start up Nios IDE

Start a new Nios II project File -> New -> Nios II C/C++ Application

Under Select Target Hardware -> SOPC Builder System PTF File -> Browse Select the ptf file from above C:/altera/Kits/CycloneIII_Starter_Kit-v7.1.0/Examples/CIII_NiosII_Small/CIII_NiosII_Small.ptf

Under Select Project Template, select the Hello LED template

Hit Finish. This should put hello_led_0 and hello_led_0_syslib in to the project list.

Right click on hello_led_0 and select System Library Properties

Select "Program never exits", "Lightweight device driver API", "Reduced device drivers", "Small C library" as we only have a few K to work with. Other options switched off. Hit OK

Right click on hello_led_0 again and select Build Project.

Right click again on hello_led_0 and select Run As -> Nios II hardware

(You may hit problems here due to not being able to generate a onchip_memory_0.hex file. This was due to the C:/altera/Kits/CycloneIII_Starter_Kit-v7.1.0/Examples/CIII_NiosII_Small directory being read only after install. Changing the properties of the directory and sub files / folders to be read write sorted this. You may want to make a copy first though incase you muck things up)

The console should end up with "Hello from Nios II". The 4 user LEDs should start to operate in a Knight Rider type scan. Unfortunately the progtam was written for 8 leds and there are only 4 so it pauses.

Change the code from:

while (1)

{

if (led & 0x81)

{

to:

while (1)

{

if (led & 0x09)

{

and hit run again and the 4 leds now operate as they should.

So that's Nios II running on a Cyclone III starter kit. Unfortunately, this version just uses the FPGA for everything and doesn't use the external Flash, SRAM or DRAM so isn't much use for uCLinux.

Stage 3a - Nios II Design with SRAM From Scratch

Next I'm going to try a Nios II design from scratch with the code running in the external SRam.

Start Quartus

File -> New Project Wizard C:/altera/local/niossram niossram niossram next -> next -> next -> Finish (should default to the correct EP3C25F324C8 device)

Start SOPC builder Tools -> SOPC Builder

System name: niossram_sopc type: verilog

This starts us off with a blank project to which we need to add the cpu, onchip ram, sram tristate bridge, sram, jtag uart and the led pio.

cpu first Nios II Processor - leave all settings on default

onchip ram Memories and Memory Controllers -> On-Chip -> On-Chip Memory (RAM or ROM) Change size to 16kBytes

sram tristate bridge Bridges and Adapters -> Memory Mapped -> Avalon-MM Tristate Bridge - leave all settings on default (should have connected to cpu above)

sram Memories and Memory Controllers -> SRAM -> Cypress CY7C1380C (identical to the ISSI IS61LPS25636A on the board) Change the size to 1MB. Connect the tristate master to the sram

jtag uart Interface Protocols -> Serial -> JTAG UART change both buffer depths to 8 and both IRQ thresholds to 4 tick both construct from registers instead of memory blocks. (should have connected to CPU)

led pio Peripherals -> Microcontroller Peripherals -> PIO (Parallel I/O) Change width to 4 bit (should have connected to CPU) rename it from pio to led_pio

That's everything connected and wired up but there will be address conflicts. System -> Auto-Assign Base Address sorts this out.

The CPU reset and exception vectors need to be set up. Go back to the cpu and change the reset vector to onchip_mem and exception vectors to ssram.

 

That's it. Hit generate.

We now have the processor. All we need to do now is connect it to all those wonderful output pins.

For the top level, I used the following verilog file (niossram.v)

// turn off superfluous verilog processor warnings

// altera message_level Level1

// altera message_off 10034 10035 10036 10037 10230 10240 10030

 

module niossram (

// inputs:

osc_clk,

reset_n,

 

// outputs:

flash_ssram_a,

flash_ssram_d,

led,

ssram_adsc_n,

ssram_bw_n,

ssram_bwe_n,

ssram_ce_n,

ssram_clk,

ssram_oe_n

);

 

input osc_clk;

input reset_n;

output [ 23: 0] flash_ssram_a;

inout [ 31: 0] flash_ssram_d;

output [ 3: 0] led;

output ssram_adsc_n;

output [ 3: 0] ssram_bw_n;

output ssram_bwe_n;

output ssram_ce_n;

output ssram_clk;

output ssram_oe_n;

 

wire [ 3: 0] led_n;

 

assign ssram_clk = osc_clk;

assign led = ~led_n;

 

niossram_sopc niossram_sopc_instance

(

.adsc_n_to_the_ssram (ssram_adsc_n),

.bw_n_to_the_ssram (ssram_bw_n),

.bwe_n_to_the_ssram (ssram_bwe_n),

.chipenable1_n_to_the_ssram (ssram_ce_n),

.address_to_the_ssram (flash_ssram_a),

.data_to_and_from_the_ssram (flash_ssram_d),

.clk (osc_clk),

.out_port_from_the_led_pio (led_n),

.outputenable_n_to_the_ssram (ssram_oe_n),

.reset_n (reset_n),

);

 

endmodule

Put this file in the main directory and then add it to the project files list. Project -> Add/Remove Files in Project... Click on the ... next to the add button, find the file, hit open and then add. (simple huh!)

This then needs to be connected to the output pins. The following tcl script will do the job.

package require ::quartus::project

 

 

set_location_assignment PIN_V9 -to osc_clk

set_location_assignment PIN_N2 -to reset_n

set_location_assignment PIN_A6 -to flash_ssram_a[20]

set_location_assignment PIN_B18 -to flash_ssram_a[21]

set_location_assignment PIN_C17 -to flash_ssram_a[22]

set_location_assignment PIN_C18 -to flash_ssram_a[23]

set_location_assignment PIN_G14 -to flash_ssram_a[24]

set_location_assignment PIN_B17 -to flash_ssram_a[25]

set_location_assignment PIN_E12 -to flash_ssram_a[1]

set_location_assignment PIN_A16 -to flash_ssram_a[2]

set_location_assignment PIN_B16 -to flash_ssram_a[3]

set_location_assignment PIN_A15 -to flash_ssram_a[4]

set_location_assignment PIN_B15 -to flash_ssram_a[5]

set_location_assignment PIN_A14 -to flash_ssram_a[6]

set_location_assignment PIN_B14 -to flash_ssram_a[7]

set_location_assignment PIN_A13 -to flash_ssram_a[8]

set_location_assignment PIN_B13 -to flash_ssram_a[9]

set_location_assignment PIN_A12 -to flash_ssram_a[10]

set_location_assignment PIN_B12 -to flash_ssram_a[11]

set_location_assignment PIN_A11 -to flash_ssram_a[12]

set_location_assignment PIN_B11 -to flash_ssram_a[13]

set_location_assignment PIN_C10 -to flash_ssram_a[14]

set_location_assignment PIN_D10 -to flash_ssram_a[15]

set_location_assignment PIN_E10 -to flash_ssram_a[16]

set_location_assignment PIN_C9 -to flash_ssram_a[17]

set_location_assignment PIN_D9 -to flash_ssram_a[18]

set_location_assignment PIN_A7 -to flash_ssram_a[19]

set_location_assignment PIN_H3 -to flash_ssram_d[0]

set_location_assignment PIN_D1 -to flash_ssram_d[1]

set_location_assignment PIN_D2 -to flash_ssram_d[19]

set_location_assignment PIN_A8 -to flash_ssram_d[2]

set_location_assignment PIN_B8 -to flash_ssram_d[3]

set_location_assignment PIN_B7 -to flash_ssram_d[4]

set_location_assignment PIN_C5 -to flash_ssram_d[5]

set_location_assignment PIN_E8 -to flash_ssram_d[6]

set_location_assignment PIN_A4 -to flash_ssram_d[7]

set_location_assignment PIN_B4 -to flash_ssram_d[8]

set_location_assignment PIN_E7 -to flash_ssram_d[9]

set_location_assignment PIN_A3 -to flash_ssram_d[10]

set_location_assignment PIN_B3 -to flash_ssram_d[11]

set_location_assignment PIN_D5 -to flash_ssram_d[12]

set_location_assignment PIN_B5 -to flash_ssram_d[13]

set_location_assignment PIN_A5 -to flash_ssram_d[14]

set_location_assignment PIN_B6 -to flash_ssram_d[15]

set_location_assignment PIN_C16 -to flash_ssram_d[16]

set_location_assignment PIN_D12 -to flash_ssram_d[17]

set_location_assignment PIN_E11 -to flash_ssram_d[18]

set_location_assignment PIN_E13 -to flash_ssram_d[20]

set_location_assignment PIN_E14 -to flash_ssram_d[21]

set_location_assignment PIN_A17 -to flash_ssram_d[22]

set_location_assignment PIN_D16 -to flash_ssram_d[23]

set_location_assignment PIN_C12 -to flash_ssram_d[24]

set_location_assignment PIN_A18 -to flash_ssram_d[25]

set_location_assignment PIN_F8 -to flash_ssram_d[26]

set_location_assignment PIN_D7 -to flash_ssram_d[27]

set_location_assignment PIN_F6 -to flash_ssram_d[28]

set_location_assignment PIN_E6 -to flash_ssram_d[29]

set_location_assignment PIN_G6 -to flash_ssram_d[30]

set_location_assignment PIN_C7 -to flash_ssram_d[31]

set_location_assignment PIN_E9 -to ssram_oe_n

set_location_assignment PIN_F9 -to ssram_ce_n

set_location_assignment PIN_F10 -to ssram_bw_n[0]

set_location_assignment PIN_F11 -to ssram_bw_n[1]

set_location_assignment PIN_F12 -to ssram_bw_n[2]

set_location_assignment PIN_F13 -to ssram_bw_n[3]

set_location_assignment PIN_F7 -to ssram_adsc_n

set_location_assignment PIN_G13 -to ssram_bwe_n

set_location_assignment PIN_P13 -to led[0]

set_location_assignment PIN_P12 -to led[1]

set_location_assignment PIN_N12 -to led[2]

set_location_assignment PIN_N9 -to led[3]

set_location_assignment PIN_A2 -to ssram_clk

set_instance_assignment -name VIRTUAL_PIN ON -to flash_ssram_a[0]

set_instance_assignment -name OUTPUT_ENABLE_GROUP 1191024410 -to led[0]

set_instance_assignment -name OUTPUT_ENABLE_GROUP 1191024410 -to led[1]

set_instance_assignment -name OUTPUT_ENABLE_GROUP 1191024410 -to led[2]

set_instance_assignment -name OUTPUT_ENABLE_GROUP 1191024410 -to led[3]

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_adsc_n

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_bw_n

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_ce_n

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_oe_n

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_bwe_n

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_clk

save this as niossrams_pins.tcl and then execute it using Tools -> TCL Scripts...

We now need to change some of the device settings to deal with the Cyclone III starter kit hardware Assignments -> Device... -> Device and Pin Options... -> Configuration Change Configuration scheme to Active Parallel -> Dual Purpose Pins Change DCLK, nCEO to Use as programming pin. All others change to Use as regular I/O

Hit compile.

Hit the Programmer button and download the new design into the Cyclone III board.

Problems with this design:

The above design is very simple and has the following issues:

  • The main fpga clk (50MHz) is simply connected through to the cpu clock and the SRAM which is not ideal. A PLL should be used to drive the cpu clock and SRAM clock from main fpga clock.
  • The SRAM tristate bridge is directly connected to cpu. It would be better to include a pipeline bridge.
  • There are a number of compiler warnings, mainly timing problems, that should be looked into.

Stage 3b - Nios II Design with SRAM - Software

Just to prove we have got something working, we will flash the LEDs again. This is a direct duplicate of the simple test above in Stage 2b so follow those instructions.

We now have flashing leds with the program running from ram. You can confirm this by switching to debug mode and looking at the dissassembly of the code. This code should reside in the sram.

Stage 4a - Nios II Design with SRAM and Flash - Hardware

A typical Nios design will have the software stored in Flash. This may be transfered to ram before it is run but we need to have the Flash connected up to the processor to allow this to happen.

Most of the process is the same as section 3 above with the addition of the Flash module and the loss of the internal ram. There are some important differences though so read carefully.

Start Quartus

File -> New Project Wizard C:/altera/local/niossramflash niossramflash niossramflash next -> next -> next -> Finish (should default to the correct EP3C25F324C8 device)

Start SOPC builder Tools -> SOPC Builder

System name: niossramflash_sopc type: verilog

This starts us off with a blank project to which we need to add the cpu, sram/flash tristate bridge, sram, jtag uart and the led pio.

cpu first Nios II Processor - leave all settings on default

sram/tristate bridge Bridges and Adapters -> Memory Mapped -> Avalon-MM Tristate Bridge - leave all settings on default (should have connected to cpu above)

sram Memories and Memory Controllers -> SRAM -> Cypress CY7C1380C (identical to the ISSI IS61LPS25636A on the board) Change the size to 1MB. Connect the tristate master to the sram

flash Memories and Memory Controllers -> Flash -> Flash Memory (CFI) Select preset Intel 128P30. This should set the address width to 23 bits and the data width to 16 bits. The timings should end up up as Setup = 25ns, Wait = 70ns, Hold=20ns. However, the example nios design has timings of Setup = 25ns, Wait = 100ns, Hold = 20ns. I'm sure there is a good reason for this so change the Wait timing to 100ns. To make the change requires changing the preset to custom. The data sheet for the flash chip (http://www.intel.com /design/flcomp/datashts/306666.htm) is not the easiest thing to read so it is difficult to check on what timing is correct. There may also be board issues which affect the timings. Connect the tristate master to the flash

sram/flash tristate bridge The data lines for the sram and flash are automatically shared by the tristate bridge but we need to tell it that the address lines for the flash and sram are shared also. Go back to the tristate bridge then click on Shared Signals. Tick address for both sram and flash.

jtag uart Interface Protocols -> Serial -> JTAG UART change both buffer depths to 8 and both IRQ thresholds to 4 tick both construct from registers instead of memory blocks. (should have connected to CPU)

led pio Peripherals -> Microcontroller Peripherals -> PIO (Parallel I/O) Change width to 4 bit (should have connected to CPU) rename it from pio to led_pio

That's everything connected and wired up but there will be address conflicts. System -> Auto-Assign Base Address sorts this out.

The CPU reset and exception vectors need to be set up. Go back to the cpu and change the reset vector to cfi_flash and exception vectors to ssram.

 

That's it. Hit generate.

We now have the processor. All we need to do now is connect it to all those wonderful output pins.

For the top level, I used the following verilog file (niossramflash.v)

// turn off superfluous verilog processor warnings

 

// altera message_level Level1

// altera message_off 10034 10035 10036 10037 10230 10240 10030

 

module niossramflash (

// inputs:

osc_clk,

reset_n,

 

// outputs:

flash_cs_n,

flash_oe_n,

flash_reset_n,

flash_ssram_a,

flash_ssram_d,

flash_wr_n,

led,

ssram_adsc_n,

ssram_bw_n,

ssram_bwe_n,

ssram_ce_n,

ssram_clk,

ssram_oe_n

);

 

output flash_cs_n;

output flash_oe_n;

output flash_reset_n;

output [ 23: 0] flash_ssram_a;

inout [ 31: 0] flash_ssram_d;

output flash_wr_n;

output [ 3: 0] led;

output ssram_adsc_n;

output [ 3: 0] ssram_bw_n;

output ssram_bwe_n;

output ssram_ce_n;

output ssram_clk;

output ssram_oe_n;

input osc_clk;

input reset_n;

 

wire [ 3: 0] led_n;

 

assign ssram_clk = osc_clk;

assign led = ~led_n;

assign flash_reset_n = reset_n;

 

niossramflash_sopc niossramflash_sopc_instance

(

.clk (osc_clk),

.reset_n (reset_n),

 

.adsc_n_to_the_ssram (ssram_adsc_n),

.bw_n_to_the_ssram (ssram_bw_n),

.bwe_n_to_the_ssram (ssram_bwe_n),

.chipenable1_n_to_the_ssram (ssram_ce_n),

.outputenable_n_to_the_ssram (ssram_oe_n),

 

.tristate_bridge_address (flash_ssram_a),

.tristate_bridge_data (flash_ssram_d),

 

.read_n_to_the_cfi_flash (flash_oe_n),

.select_n_to_the_cfi_flash (flash_cs_n),

.write_n_to_the_cfi_flash (flash_wr_n),

 

.out_port_from_the_led_pio (led_n),

);

 

endmodule

Put this file in the main directory and then add it to the project files list. Project -> Add/Remove Files in Project... Click on the ... next to the add button, find the file, hit open and then add. (simple huh!)

This then needs to be connected to the output pins. The following tcl script will do the job.

package require ::quartus::project

 

 

set_location_assignment PIN_V9 -to osc_clk

set_location_assignment PIN_N2 -to reset_n

set_location_assignment PIN_D18 -to flash_wr_n

set_location_assignment PIN_E2 -to flash_cs_n

set_location_assignment PIN_D17 -to flash_oe_n

set_location_assignment PIN_C3 -to flash_reset_n

set_location_assignment PIN_A6 -to flash_ssram_a[20]

set_location_assignment PIN_B18 -to flash_ssram_a[21]

set_location_assignment PIN_C17 -to flash_ssram_a[22]

set_location_assignment PIN_C18 -to flash_ssram_a[23]

set_location_assignment PIN_G14 -to flash_ssram_a[24]

set_location_assignment PIN_B17 -to flash_ssram_a[25]

set_location_assignment PIN_E12 -to flash_ssram_a[1]

set_location_assignment PIN_A16 -to flash_ssram_a[2]

set_location_assignment PIN_B16 -to flash_ssram_a[3]

set_location_assignment PIN_A15 -to flash_ssram_a[4]

set_location_assignment PIN_B15 -to flash_ssram_a[5]

set_location_assignment PIN_A14 -to flash_ssram_a[6]

set_location_assignment PIN_B14 -to flash_ssram_a[7]

set_location_assignment PIN_A13 -to flash_ssram_a[8]

set_location_assignment PIN_B13 -to flash_ssram_a[9]

set_location_assignment PIN_A12 -to flash_ssram_a[10]

set_location_assignment PIN_B12 -to flash_ssram_a[11]

set_location_assignment PIN_A11 -to flash_ssram_a[12]

set_location_assignment PIN_B11 -to flash_ssram_a[13]

set_location_assignment PIN_C10 -to flash_ssram_a[14]

set_location_assignment PIN_D10 -to flash_ssram_a[15]

set_location_assignment PIN_E10 -to flash_ssram_a[16]

set_location_assignment PIN_C9 -to flash_ssram_a[17]

set_location_assignment PIN_D9 -to flash_ssram_a[18]

set_location_assignment PIN_A7 -to flash_ssram_a[19]

set_location_assignment PIN_H3 -to flash_ssram_d[0]

set_location_assignment PIN_D1 -to flash_ssram_d[1]

set_location_assignment PIN_D2 -to flash_ssram_d[19]

set_location_assignment PIN_A8 -to flash_ssram_d[2]

set_location_assignment PIN_B8 -to flash_ssram_d[3]

set_location_assignment PIN_B7 -to flash_ssram_d[4]

set_location_assignment PIN_C5 -to flash_ssram_d[5]

set_location_assignment PIN_E8 -to flash_ssram_d[6]

set_location_assignment PIN_A4 -to flash_ssram_d[7]

set_location_assignment PIN_B4 -to flash_ssram_d[8]

set_location_assignment PIN_E7 -to flash_ssram_d[9]

set_location_assignment PIN_A3 -to flash_ssram_d[10]

set_location_assignment PIN_B3 -to flash_ssram_d[11]

set_location_assignment PIN_D5 -to flash_ssram_d[12]

set_location_assignment PIN_B5 -to flash_ssram_d[13]

set_location_assignment PIN_A5 -to flash_ssram_d[14]

set_location_assignment PIN_B6 -to flash_ssram_d[15]

set_location_assignment PIN_C16 -to flash_ssram_d[16]

set_location_assignment PIN_D12 -to flash_ssram_d[17]

set_location_assignment PIN_E11 -to flash_ssram_d[18]

set_location_assignment PIN_E13 -to flash_ssram_d[20]

set_location_assignment PIN_E14 -to flash_ssram_d[21]

set_location_assignment PIN_A17 -to flash_ssram_d[22]

set_location_assignment PIN_D16 -to flash_ssram_d[23]

set_location_assignment PIN_C12 -to flash_ssram_d[24]

set_location_assignment PIN_A18 -to flash_ssram_d[25]

set_location_assignment PIN_F8 -to flash_ssram_d[26]

set_location_assignment PIN_D7 -to flash_ssram_d[27]

set_location_assignment PIN_F6 -to flash_ssram_d[28]

set_location_assignment PIN_E6 -to flash_ssram_d[29]

set_location_assignment PIN_G6 -to flash_ssram_d[30]

set_location_assignment PIN_C7 -to flash_ssram_d[31]

set_location_assignment PIN_E9 -to ssram_oe_n

set_location_assignment PIN_F9 -to ssram_ce_n

set_location_assignment PIN_F10 -to ssram_bw_n[0]

set_location_assignment PIN_F11 -to ssram_bw_n[1]

set_location_assignment PIN_F12 -to ssram_bw_n[2]

set_location_assignment PIN_F13 -to ssram_bw_n[3]

set_location_assignment PIN_F7 -to ssram_adsc_n

set_location_assignment PIN_G13 -to ssram_bwe_n

set_location_assignment PIN_P13 -to led[0]

set_location_assignment PIN_P12 -to led[1]

set_location_assignment PIN_N12 -to led[2]

set_location_assignment PIN_N9 -to led[3]

set_location_assignment PIN_A2 -to ssram_clk

set_instance_assignment -name VIRTUAL_PIN ON -to flash_ssram_a[0]

set_instance_assignment -name OUTPUT_ENABLE_GROUP 1191024410 -to led[0]

set_instance_assignment -name OUTPUT_ENABLE_GROUP 1191024410 -to led[1]

set_instance_assignment -name OUTPUT_ENABLE_GROUP 1191024410 -to led[2]

set_instance_assignment -name OUTPUT_ENABLE_GROUP 1191024410 -to led[3]

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_adsc_n

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_bw_n

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_ce_n

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_oe_n

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_bwe_n

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_clk

save this as niossramsflash_pins.tcl and then execute it using Tools -> TCL Scripts...

We now need to change some of the device settings to deal with the Cyclone III starter kit hardware Assignments -> Device... -> Device and Pin Options... -> Configuration Change Configuration scheme to Active Parallel -> Dual Purpose Pins Change DCLK, nCEO to Use as programming pin. All others change to Use as regular I/O

Hit compile.

Hit the Programmer button and download the new design into the Cyclone III board.

Problems with this design:

The above design is very simple and has the following issues:

  • The main fpga clk (50MHz) is simply connected through to the cpu clock and the SRAM which is not ideal. A PLL should be used to drive the cpu clock and SRAM clock from main fpga clock.
  • The SRAM tristate bridge is directly connected to cpu. It would be better to include a pipeline bridge.
  • There are a number of compiler warnings, mainly timing problems, that should be looked into.
  • It is interesting to note that the flash chips Clock, Wait and Adv pins are not used in this design at all. This is the same as the way the standard Altera design connects the flash chip up and appears to work fine.

Stage 4b - Nios II Design with SRAM and Flash - Software

Just to prove we have got something working, we will flash the LEDs again. This is a direct duplicate of the simple test above in Stage 2b so follow those instructions.

A more important test is to perform a memory check on the flash and sram.

In Nios EDS start a new Nios Application as before, this time using the memtest template. As we now have a lot of space it isn't necessary to tick the small C library etc options.

Build and run the application and you can check the operation of the ram and the flash. Note that the name for the flash is /dev/cfi_flash if you have left the naming as default for the flash in SOPC builder.

Stage 4c - Sort out the Clocks

The system is currently running directly from the input 50MHz clock. Nios II can run faster than this on Cyclone III and we ought to sort out the SRAM clock as well.

Go back into SOPC builder and press filter (bottom right). Select clocks so we can see what is going on. Currently, the clock source (which should have appeared) drives all the modules.

Add a PLL (Phase Locked Loop) PLL -> PLL Click on Launch Altera's ALTPLL MegaWizard Page 1 - Speed grade 8, 50MHz, Select the PLL type automatically, Use the feedback path inside the PLL, In Normal Mode, c0 Page 2 - nothing selected (default) Page 3 - auto (default) Page 4 - nothing selected (default) Page 5 - nothing selected (default) Page 6 - c0 - Use this clock, 2, 1, 0ps, 50% (actual setting should be 100MHz) Page 7 - c1 - Use this clock, 2, 1, -2000ps, 50% (actual setting should be 100MHz) Page 8 - c2 - nothing selected (default) Page 9 - c3 - nothing selected (default) Page 10 - c4 - nothing selected (default) Page 11 - nothing selected (default) Page 12 - nothing selected (default) Rename C0 to cpu_clk Rename C1 to ssram_clk (this clock goes externally to the sram. The interface to the sram is driven by the cpu_clk) Connect C0 (cpu_clk) to everything so that we are now running at 100MHz Auto assign base addresses again.

 

Regenerate SOPC

Modify niossramflash.v to the following:

// turn off superfluous verilog processor warnings

 

// altera message_level Level1

// altera message_off 10034 10035 10036 10037 10230 10240 10030

 

module niossramflash (

// inputs:

osc_clk,

reset_n,

 

// outputs:

flash_cs_n,

flash_oe_n,

flash_reset_n,

flash_ssram_a,

flash_ssram_d,

flash_wr_n,

led,

ssram_adsc_n,

ssram_bw_n,

ssram_bwe_n,

ssram_ce_n,

ssram_clk,

ssram_oe_n

);

 

output flash_cs_n;

output flash_oe_n;

output flash_reset_n;

output [ 23: 0] flash_ssram_a;

inout [ 31: 0] flash_ssram_d;

output flash_wr_n;

output [ 3: 0] led;

output ssram_adsc_n;

output [ 3: 0] ssram_bw_n;

output ssram_bwe_n;

output ssram_ce_n;

output ssram_clk;

output ssram_oe_n;

input osc_clk;

input reset_n;

 

wire [ 3: 0] led_n;

 

assign led = ~led_n;

assign flash_reset_n = reset_n;

 

niossramflash_sopc niossramflash_sopc_instance

(

.clk (osc_clk),

.reset_n (reset_n),

.ssram_clk (ssram_clk),

 

.adsc_n_to_the_ssram (ssram_adsc_n),

.bw_n_to_the_ssram (ssram_bw_n),

.bwe_n_to_the_ssram (ssram_bwe_n),

.chipenable1_n_to_the_ssram (ssram_ce_n),

.outputenable_n_to_the_ssram (ssram_oe_n),

 

.tristate_bridge_address (flash_ssram_a),

.tristate_bridge_data (flash_ssram_d),

 

.read_n_to_the_cfi_flash (flash_oe_n),

.select_n_to_the_cfi_flash (flash_cs_n),

.write_n_to_the_cfi_flash (flash_wr_n),

 

.out_port_from_the_led_pio (led_n),

);

 

endmodule

Recompile project

Switch to Nios II EDS and recompile and run the LED test program. The LEDs should now flash twice as fast as they did before.

We still have the issue of all the timing errors on compilation though.

Stage 5a - Nios II Design wih SRAM / Flash and SDRAM - Hardware

There is a good amount of SDRAM on the Cyclone III starter kit board (32MB) so we want to get it operational. It is also necessary if want to install uClinux as there is not enough SRAM to just use that.

I had problems adding the DDR SDRAM initially as the module wasn't available within SOPC. The problem turned out to be due to the SOPC path not pointing to the MegaCore IP installeded initially. Adding the correct path (Tools -> Options... -> IP Search Path) followed by a refresh (File -> Refresh Component List) made them appear.

Duplicate Stage 4 with exception of making the LED pio only 1 bit wide. Its not possible to have a 4 bit wide LED pio as the LED pins are too close to the SDRAM pins leading to some sort of overload. Call the project niossramflashsdram.

On the cpu, change the reset vector to cfi_flash 0x0. Change the Exception vector to ssram 0x20.

In addition, we need to add the DDR SDRAM interface Memory and Memory Controllers -> SDRAM -> DDR SDRAM High Performance Select and load the PSC A2S56D40CTP-G5 (some Altera designs for the board use a Micron part, this has the same pin out but different timings) Set Speed Grade to 8 Set PLL Refererence Frequency to 50MHz Set Memory Clock Frequency to 100MHz Set Local Interface Clock Frequency to Full (Local Interface Width should be 32 bits) Hit finish Rename part to ddr_sdram

Now the SDRAM is running at the same 100MHz as the main processor but it is on its own clock. The phase could therefore be out. It is therefore necessary to add a Clock Crossing Bridge to allow access from the cpu. (I believe this to be correct, it may be possible to get everything running off the same clock - and I've had some success doing this - but a clock crossing bridge is safer. Comments please from any experts out there) Bridges and Adapters -> Memory Mapped -> Avalon-MM Clock Crossing Bridge Master to Slave FIFO depth - 8 Slave to Master FIFO depth - 64 Data Width - 32 Rename part to cpu_ddr_clock_bridge

Note: The flash will run at 133MHz so the speed could be increased if required. As there is a Clock Crossing Bridge, having a mismatch in clock speeds isn't a problem though there may be performance issues.

Add a timer as well Peripherals -> Microcontroller Peripherals -> Interval Timer Period - 10ms Presets - Full featured

There are lots of connections. Make them as per the following diagram:

 

Note that there are a couple of "Multiple ports named" errors. These can be ignored (I believe).

Change the address map to match the above. The exact values don't normally matter but use the above as there is an advantage in doing so as we shall see shortly.

Change the IRQ numbers to those above.

Hit the generate button.

Create a niossramflashsdram.v and fill it with the following:

 

// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030

module niossramflashsdram (
// inputs:
osc_clk,
reset_n,

// outputs:
flash_cs_n,
flash_oe_n,
flash_reset_n,
flash_ssram_a,
flash_ssram_d,
flash_wr_n,
led,
ssram_adsc_n,
ssram_bw_n,
ssram_bwe_n,
ssram_ce_n,
ssram_clk,
ssram_oe_n,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_ras_n,
mem_we_n,
);
output flash_cs_n;
output flash_oe_n;
output flash_reset_n;
output [ 23: 0] flash_ssram_a;
inout [ 31: 0] flash_ssram_d;
output flash_wr_n;
output [ 0: 0] led;
output ssram_adsc_n;
output [ 3: 0] ssram_bw_n;
output ssram_bwe_n;
output ssram_ce_n;
output ssram_clk;
output ssram_oe_n;
input osc_clk;
input reset_n;
output [ 12: 0] mem_addr;
output [ 1: 0] mem_ba;
output mem_cas_n;
output mem_cke;
inout mem_clk;
inout mem_clk_n;
output mem_cs_n;
output [ 1: 0] mem_dm;
inout [ 15: 0] mem_dq;
inout [ 1: 0] mem_dqs;
output mem_ras_n;
output mem_we_n;
wire [ 0: 0] led_n;
assign led = ~led_n;
assign flash_reset_n = reset_n;

niossramflashsdram_sopc niossramflashsdram_sopc_instance
(
.clk (osc_clk),
.reset_n (reset_n),
.ssram_clk (ssram_clk),
.adsc_n_to_the_ssram (ssram_adsc_n),
.bw_n_to_the_ssram (ssram_bw_n),
.bwe_n_to_the_ssram (ssram_bwe_n),
.chipenable1_n_to_the_ssram (ssram_ce_n),
.outputenable_n_to_the_ssram (ssram_oe_n),
.tristate_bridge_address (flash_ssram_a),
.tristate_bridge_data (flash_ssram_d),
.read_n_to_the_cfi_flash (flash_oe_n),
.select_n_to_the_cfi_flash (flash_cs_n),
.write_n_to_the_cfi_flash (flash_wr_n),
.mem_addr_from_the_ddr_sdram (mem_addr),
.mem_ba_from_the_ddr_sdram (mem_ba),
.mem_cas_n_from_the_ddr_sdram (mem_cas_n),
.mem_cke_from_the_ddr_sdram (mem_cke),
.mem_clk_n_to_and_from_the_ddr_sdram (mem_clk_n),
.mem_clk_to_and_from_the_ddr_sdram (mem_clk),
.mem_cs_n_from_the_ddr_sdram (mem_cs_n),
.mem_dm_from_the_ddr_sdram (mem_dm),
.mem_dq_to_and_from_the_ddr_sdram (mem_dq),
.mem_dqs_to_and_from_the_ddr_sdram (mem_dqs),
.mem_ras_n_from_the_ddr_sdram (mem_ras_n),
.mem_we_n_from_the_ddr_sdram (mem_we_n),
.global_reset_n_to_the_ddr_sdram (reset_n),
.out_port_from_the_led_pio (led_n),
);
endmodule

 


Connect everything up using the following TCL file.

 

package require ::quartus::project

set_location_assignment PIN_V9 -to osc_clk
set_location_assignment PIN_N2 -to reset_n
set_location_assignment PIN_D18 -to flash_wr_n
set_location_assignment PIN_E2 -to flash_cs_n
set_location_assignment PIN_D17 -to flash_oe_n
set_location_assignment PIN_C3 -to flash_reset_n
set_location_assignment PIN_A6 -to flash_ssram_a[20]
set_location_assignment PIN_B18 -to flash_ssram_a[21]
set_location_assignment PIN_C17 -to flash_ssram_a[22]
set_location_assignment PIN_C18 -to flash_ssram_a[23]
set_location_assignment PIN_G14 -to flash_ssram_a[24]
set_location_assignment PIN_B17 -to flash_ssram_a[25]
set_location_assignment PIN_E12 -to flash_ssram_a[1]
set_location_assignment PIN_A16 -to flash_ssram_a[2]
set_location_assignment PIN_B16 -to flash_ssram_a[3]
set_location_assignment PIN_A15 -to flash_ssram_a[4]
set_location_assignment PIN_B15 -to flash_ssram_a[5]
set_location_assignment PIN_A14 -to flash_ssram_a[6]
set_location_assignment PIN_B14 -to flash_ssram_a[7]
set_location_assignment PIN_A13 -to flash_ssram_a[8]
set_location_assignment PIN_B13 -to flash_ssram_a[9]
set_location_assignment PIN_A12 -to flash_ssram_a[10]
set_location_assignment PIN_B12 -to flash_ssram_a[11]
set_location_assignment PIN_A11 -to flash_ssram_a[12]
set_location_assignment PIN_B11 -to flash_ssram_a[13]
set_location_assignment PIN_C10 -to flash_ssram_a[14]
set_location_assignment PIN_D10 -to flash_ssram_a[15]
set_location_assignment PIN_E10 -to flash_ssram_a[16]
set_location_assignment PIN_C9 -to flash_ssram_a[17]
set_location_assignment PIN_D9 -to flash_ssram_a[18]
set_location_assignment PIN_A7 -to flash_ssram_a[19]
set_location_assignment PIN_H3 -to flash_ssram_d[0]
set_location_assignment PIN_D1 -to flash_ssram_d[1]
set_location_assignment PIN_D2 -to flash_ssram_d[19]
set_location_assignment PIN_A8 -to flash_ssram_d[2]
set_location_assignment PIN_B8 -to flash_ssram_d[3]
set_location_assignment PIN_B7 -to flash_ssram_d[4]
set_location_assignment PIN_C5 -to flash_ssram_d[5]
set_location_assignment PIN_E8 -to flash_ssram_d[6]
set_location_assignment PIN_A4 -to flash_ssram_d[7]
set_location_assignment PIN_B4 -to flash_ssram_d[8]
set_location_assignment PIN_E7 -to flash_ssram_d[9]
set_location_assignment PIN_A3 -to flash_ssram_d[10]
set_location_assignment PIN_B3 -to flash_ssram_d[11]
set_location_assignment PIN_D5 -to flash_ssram_d[12]
set_location_assignment PIN_B5 -to flash_ssram_d[13]
set_location_assignment PIN_A5 -to flash_ssram_d[14]
set_location_assignment PIN_B6 -to flash_ssram_d[15]
set_location_assignment PIN_C16 -to flash_ssram_d[16]
set_location_assignment PIN_D12 -to flash_ssram_d[17]
set_location_assignment PIN_E11 -to flash_ssram_d[18]
set_location_assignment PIN_E13 -to flash_ssram_d[20]
set_location_assignment PIN_E14 -to flash_ssram_d[21]
set_location_assignment PIN_A17 -to flash_ssram_d[22]
set_location_assignment PIN_D16 -to flash_ssram_d[23]
set_location_assignment PIN_C12 -to flash_ssram_d[24]
set_location_assignment PIN_A18 -to flash_ssram_d[25]
set_location_assignment PIN_F8 -to flash_ssram_d[26]
set_location_assignment PIN_D7 -to flash_ssram_d[27]
set_location_assignment PIN_F6 -to flash_ssram_d[28]
set_location_assignment PIN_E6 -to flash_ssram_d[29]
set_location_assignment PIN_G6 -to flash_ssram_d[30]
set_location_assignment PIN_C7 -to flash_ssram_d[31]
set_location_assignment PIN_E9 -to ssram_oe_n
set_location_assignment PIN_F9 -to ssram_ce_n
set_location_assignment PIN_F10 -to ssram_bw_n[0]
set_location_assignment PIN_F11 -to ssram_bw_n[1]
set_location_assignment PIN_F12 -to ssram_bw_n[2]
set_location_assignment PIN_F13 -to ssram_bw_n[3]
set_location_assignment PIN_F7 -to ssram_adsc_n
set_location_assignment PIN_G13 -to ssram_bwe_n

set_location_assignment PIN_U2 -to mem_clk
set_location_assignment PIN_V2 -to mem_clk_n
set_location_assignment PIN_V1 -to mem_cs_n
set_location_assignment PIN_R13 -to mem_cke
set_location_assignment PIN_U1 -to mem_addr[0]
set_location_assignment PIN_U5 -to mem_addr[1]
set_location_assignment PIN_U7 -to mem_addr[2]
set_location_assignment PIN_U8 -to mem_addr[3]
set_location_assignment PIN_P8 -to mem_addr[4]
set_location_assignment PIN_P7 -to mem_addr[5]
set_location_assignment PIN_P6 -to mem_addr[6]
set_location_assignment PIN_T14 -to mem_addr[7]
set_location_assignment PIN_T13 -to mem_addr[8]
set_location_assignment PIN_V13 -to mem_addr[9]
set_location_assignment PIN_U17 -to mem_addr[10]
set_location_assignment PIN_V17 -to mem_addr[11]
set_location_assignment PIN_U16 -to mem_addr[12]
set_location_assignment PIN_V11 -to mem_ba[0]
set_location_assignment PIN_V12 -to mem_ba[1]
set_location_assignment PIN_V16 -to mem_ras_n
set_location_assignment PIN_T4 -to mem_cas_n
set_location_assignment PIN_U15 -to mem_we_n
set_location_assignment PIN_U4 -to mem_dq[0]
set_location_assignment PIN_V4 -to mem_dq[1]
set_location_assignment PIN_R8 -to mem_dq[2]
set_location_assignment PIN_V5 -to mem_dq[3]
set_location_assignment PIN_P9 -to mem_dq[4]
set_location_assignment PIN_U6 -to mem_dq[5]
set_location_assignment PIN_V6 -to mem_dq[6]
set_location_assignment PIN_V7 -to mem_dq[7]
set_location_assignment PIN_U13 -to mem_dq[8]
set_location_assignment PIN_U12 -to mem_dq[9]
set_location_assignment PIN_U11 -to mem_dq[10]
set_location_assignment PIN_V15 -to mem_dq[11]
set_location_assignment PIN_U14 -to mem_dq[12]
set_location_assignment PIN_R11 -to mem_dq[13]
set_location_assignment PIN_P10 -to mem_dq[14]
set_location_assignment PIN_V14 -to mem_dq[15]
set_location_assignment PIN_U3 -to mem_dqs[0]
set_location_assignment PIN_T8 -to mem_dqs[1]
set_location_assignment PIN_V3 -to mem_dm[0]
set_location_assignment PIN_V8 -to mem_dm[1]

set_location_assignment PIN_P13 -to led[0]
//set_location_assignment PIN_T1 -to led[1]
//set_location_assignment PIN_N12 -to led[2]
//set_location_assignment PIN_N9 -to led[3]

set_location_assignment PIN_A2 -to ssram_clk
set_instance_assignment -name VIRTUAL_PIN ON -to flash_ssram_a[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1191024410 -to led[0]
//set_instance_assignment -name OUTPUT_ENABLE_GROUP 1191024410 -to led[1]
//set_instance_assignment -name OUTPUT_ENABLE_GROUP 1191024410 -to led[2]
//set_instance_assignment -name OUTPUT_ENABLE_GROUP 1191024410 -to led[3]

set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_adsc_n
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_bw_n
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_ce_n
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_oe_n
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_bwe_n
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ssram_clk
set_location_assignment PLL_4 -to "*|ddr_sdram:the_ddr_sdram|*|pll1"
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_clk[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_clk[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_clk_n[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_clk_n[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_cs_n[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_cs_n[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_cke[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_cke[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_addr[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_addr[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_addr[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_addr[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_addr[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_addr[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_addr[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_addr[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_addr[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_addr[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_addr[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_addr[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_addr[12]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_addr[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_addr[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_addr[2]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_addr[3]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_addr[4]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_addr[5]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_addr[6]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_addr[7]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_addr[8]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_addr[9]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_addr[10]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_addr[11]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_addr[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ba[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_ba[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_ba[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ras_n
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_ras_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_cas_n
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_cas_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_we_n
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_we_n
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dq[15]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[2]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[3]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[4]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[5]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[6]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[7]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[8]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[9]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[10]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[11]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[12]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[13]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[14]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dq[15]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[2]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[3]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[4]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[5]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[6]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[7]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[8]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[9]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[10]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[11]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[12]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[13]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[14]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dq[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dqs[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dqs[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dqs[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dqs[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dqs[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dqs[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dm[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to mem_dm[1]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dm[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1244174944 -to mem_dm[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dm[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to mem_dm[1]

 

Recompile the whole project.

There should now be far fewer timing faults with the remainder due to a PLL problem. Unfortunately, I don't have a solution to this.

Stage 5b - Nios II Design wih SRAM / Flash and SDRAM - Software

Now, it is possible to compile and run the memory test programs to test the design as before but there is a far more interesting thing we can try (if you have used the address settings shown above).

Download File:ZImage cycloneIII embedded evaluation kit web server.gz and save it in the same directory as the above design. File was generated by hippo I believe so thank him.

Bring up two Nios2 command shells Start -> Programs -> Altera -> Nios II EDS 7.2 -> Nios II Command Shell

In the both windows change to the directory with the above design.

In the first window, we will download the design into the starter kit using the command line:

[SOPC Builder]$ nios2-configure-sof niossramflashsdram_time_limited.sof

This should produce something like the following:

Searching for SOF file:
in .
niossramflashsdram_time_limited.sof
File niossramflashsdram_time_limited.sof contains one or more time-limited
megafunctions that support the OpenCore Plus feature that will not work after the
hardware evaluation time expires. Refer to the Messages window for evaluation time
details.

Info: SRAM Object File niossramflashsdram_time_limited.sof contains time-limited
megafunction that supports OpenCore Plus feature -- Vendor: 0x6AF7, Product: 0x00A2

Info: SRAM Object File niossramflashsdram_time_limited.sof contains time-limited
megafunction that supports OpenCore Plus feature -- Vendor: 0x6AF7, Product: 0x00BE

Info: *******************************************************************
Info: Running Quartus II Programme
Info: Command: quartus_pgm --no_banner --mode=jtag --cable=2 -o p;niossramflashs
dram_time_limited.sof
Info: Using programming cable "USB-Blaster [USB-0]"
Info: Started Programmer operation at Thu May 15 10:37:42 2008
Info: Configuring device index 1
Info: Device 1 contains JTAG ID code 0x020F30DD
Info: Configuration succeeded -- 1 device(s) configured
Info: Successfully performed operation(s)
Info: Ended Programmer operation at Thu May 15 10:37:43 2008
Please enter i for info and q to quit:

The design has now been downloaded into the Cyclone chip and a connection has been made to keep the design alive due to the license restriction on the Nios II. If you quit out of the program, it will stop this connection and the design / processor will stop operating.

Switch to the second command shell.

Type the following to download the software image into the processor:

[SOPC Builder]$ nios2-download -g zImage_cycloneIII_embedded_evaluation_kit_web_server

This will produce something like the following:

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Pausing target processor: OK
Initializing CPU cache (if present)
OK
Downloaded 1206KB in 14.6s (82.6KB/s)
Verified OK
Starting processor at address 0x00500000

All we need to do now is connect to the JTAG terminal to see what has happened.

Using the same window, type the following:

[SOPC Builder]$ nios2-terminal

This results in the following:

nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)

Uncompressing Linux... Ok, booting the kernel.
Linux version 2.6.19-uc1-g7e2efdd1 <a rel="freelink" href="mailto:(thomas@darkstar.wytron.com.tw)" >(thomas@darkstar.wytron.com.tw) (gcc version
3.4.6) #21 PREEMPT Wed Mar 19 09:00:11 CST 2008

uClinux/Nios II
Altera Nios II support (C) 2004 Microtronix Datacom Ltd.

setup_arch: No persistant network settings signature at 04FF0000
Built 1 zonelists. Total pages: 8128
Kernel command line:
PID hash table entries: 128 (order: 7, 512 bytes)
Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)
Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)
Memory available: 30312k/32768k RAM, 0k/0k ROM (1471k kernel code, 687k data)
Mount-cache hash table entries: 512
NET: Registered protocol family 16
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 1024 (order: 0, 4096 bytes)
TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
TCP: Hash tables configured (established 1024 bind 1024)
TCP reno registered
io scheduler noop registered
io scheduler deadline registered (default)
Serial: JTAG UART driver $Revision: 1.3 $
ttyJ0 at MMIO 0x88002000 (irq = 10) is a jtag_uart
dm9000 Ethernet Driver
TCP cubic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
Freeing unused kernel memory: 576k freed (0x17c000 - 0x20b000)
Shell invoked to run file: /etc/rc
Command: hostname uClinux
Command: mount -t proc proc /proc
Command: mount -t sysfs sysfs /sys
Command: mount -t usbfs none /proc/bus/usb
mount: Mounting none on /proc/bus/usb failed: No such file or directory
Command: mkdir /var/tmp
Command: mkdir /var/log
Command: mkdir /var/run
Command: mkdir /var/lock
Command: mkdir /var/empty
Command: ifconfig lo 127.0.0.1
Command: route add -net 127.0.0.0 netmask 255.0.0.0 lo
Command: cat /etc/motd
Welcome to Linux

For further information check:

http://www.uclinux.org/

 

Execution Finished, Exiting

 

Sash command shell (version 1.1.1)

 

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