DSP Basic Design Examples
FFT to iFFT with Natural input and output order using Cosine data design example
Overview
This basic design example with Modelsim simulation demonstrates the implementation of FFT and iFFT operation with input and output orders configured in Natural mode. Ideal Cosine data is fed into the FFT block and the output from the FFT is connected to the iFFT for data verification. If both the FFT and iFFT are operating as expected, Cosine data will be recovered and observed at the iFFT output.
The design also comes with example test bench and TCL files to run simulation in Modelsim for reference. Note that ROM is used to store the Cosine data in this example just for demo purpose. You should create your own mechanism to perform the data and FFT controls.
To run the simulation, do the following:
1. Unzip the files
2. Change the Modelsim directory to the "\fft0\simulation\mentor" folder
3. Type "source msim_setup.tcl"
4. Type "ld" to compile
5. Type "do wave.do" to populate the waveform
6. Type "run -all" to start the simulation
Design File
FFT to iFFT with Natural input and output order using Cosine data design example Qstd 17.0 (ZIP)
Design Specifications
The table below lists the specifications for this design:
Attribute | Specification |
Device | Cyclone V |
Quartus version | Quartus Prime v17.0 Std Edition |
Modelsim version | ModelSim - Intel FPGA Edition 10.5b |
Data pattern | Cosine |
Number of channels | 1 |
IP used | FFT, iFFT |
FFT to iFFT with Natural and Digit Reverse I/O orders using Cosine data design example
Overview
This basic design example with Modelsim simulation demonstrates the implementation of FFT (Natural input and Digit Reverse output) and iFFT (Digit Reverse input and Natural output) operation. Ideal Cosine data is fed into the FFT block and the output from the FFT is connected to the iFFT for data verification. When both the FFT and iFFT are operating as expected, Cosine data will be recovered and observed at the iFFT output.
The design also comes with example test bench and TCL files to run simulation in Modelsim for reference. Note that ROM is used to store the Cosine data in this example just for demo purpose. You should create your own mechanism to perform the data and FFT controls.
To run the simulation, do the following:
1. Unzip the files
2. Change the Modelsim directory to the "\fft0\simulation\mentor" folder
3. Type "source msim_setup.tcl"
4. Type "ld" to compile
5. Type "do wave.do" to populate the waveform
6. Type "run -all" to start the simulation
Design File
Design Specifications
The table below lists the specifications for this design:
Attribute | Specification |
Device | Cyclone V |
Quartus version | Quartus Prime v17.0 Std Edition |
Modelsim version | ModelSim - Intel FPGA Edition 10.5b |
Data pattern | Cosine |
Number of channels | 1 |
IP used | FFT, iFFT |
CVGT Devkit FFT to iFFT with Natural input and output orders using Cosine data design example
Overview
This basic design example demonstrates the implementation of FFT and iFFT operation with input and output orders configured in Natural mode. Ideal Cosine data is fed into the FFT block and the output from the FFT is connected to the iFFT for data verification. This design has been tested on the Cyclone V GT FPGA Development Kit . When both the FFT and iFFT are operating as expected, Cosine data will be recovered and observed at the iFFT output.
Note that ROM is used to store the Cosine data in this example just for demo purpose. You should create your own mechanism to perform the data and FFT controls.
To run the design, do the following steps:
1. Extract the project QAR
2. Compile the design and program the SOF file into the Cyclone V device
3. Open the Signaltap (stp1.stp) and establish connection to the device
4. Open the ISSP editor and link to the device
5. Write 1'b1 to source[0] and then 1'b0 to source[0] in ISSP editor to generate a reset to the system
6. You should observe Cosine data at the iFFT output in two's complement format
Design File
Design Specifications
The table below lists the specifications for this design:
Attribute | Specification |
Device | Cyclone V |
Quartus version | Quartus Prime v17.0 Std Edition |
Development Kit | Cyclone V GT FPGA Development Kit |
Data pattern | Cosine |
Number of channels | 1 |
IP used | FFT, iFFT |
CVGT Devkit FFT to iFFT with Natural and Digit Reverse I/O orders using Cosine data design example
Overview
This basic design example demonstrates the implementation of FFT (Natural input and Digit Reverse output) and iFFT (Digit Reverse input and Natural output) operation. Ideal Cosine data is fed into the FFT block and the output from the FFT is connected to the iFFT for data verification. This design has been tested on the Cyclone V GT FPGA Development Kit . When both the FFT and iFFT are operating as expected, Cosine data will be recovered and observed at the iFFT output.
Note that ROM is used to store the Cosine data in this example just for demo purpose. You should create your own mechanism to perform the data and FFT controls.
To run the design, do the following steps:
1. Extract the project QAR
2. Compile the design and program the SOF file into the Cyclone V device
3. Open the Signaltap (stp1.stp) and establish connection to the device
4. Open the ISSP editor and link to the device
5. Write 1'b1 to source[0] and then 1'b0 to source[0] in ISSP editor to generate a reset to the system
6. You should observe Cosine data at the iFFT output in two's complement format
Design File
Design Specifications
The table below lists the specifications for this design:
Attribute | Specification |
Device | Cyclone V |
Quartus version | Quartus Prime v17.0 Std Edition |
Development Kit | Cyclone V GT FPGA Development Kit |
Data pattern | Cosine |
Number of channels | 1 |
IP used | FFT, iFFT |