Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your profile.
Das u-boot is a fancy bootloader with net support and scripting capabilities.
This is a new approach to port u-boot for nios2 boards. We use device tree blob generated from the sopcinfo file to control u-boot. The same dtb can be used to control Linux.
This feature is available in the u-boot mainline, prepared for v2016.01. This is not compatible with the v2013.01 based Altera release.
You can clone the git from denx server and create the branch,
$ git clone git://git.denx.de/u-boot.git
$ cd u-boot
Take 10m50 devboard GHRD 15.1 with 16550 UART as an example,
Program the Max10 device with the pof from max10_devkit_ghrd_15.1.zip on the rocketboards.org,
$ quartus_pgm --mode=jtag -o p\;ghrd_10m50daf484c6ges_top.pof
Configure for 10m50 devboard and build,
$ export CROSS_COMPILE=nios2-elf- (or nios2-linux-gnu-)
$ make 10m50_defconfig
$ make
Now you will have u-boot-dtb.bin as final binary output. We will use this to program the flash.
Open another terminal to connect the serial port, eg I use picocom,
$ picocom -b 115200 /dev/ttyUSB0
Open yet another terminal to run gdb-server,
$ nios2-gdb-server --tcpport 2342 --tcppersist
Run gdb and download the binary to SDRAM at 0xcc000000,
$ nios2-elf-gdb
(gdb) target remote localhost:2342
(gdb) restore u-boot-dtb.bin binary 0xcc000000
(gdb) jump *0xcc000000
Now you will see the u-boot prompt on the serial, erase and program the QSPI flash at 0xf4000000,
==> erase f4000000 +80000
==> cp.b cc000000 f4000000 80000
You may use this method to program the Linux kernel and rootfs images.
Take 3c120 devboard GHRD with JATG UART as an example,
Configure for 3c120 devboard and build,
$ export CROSS_COMPILE=nios2-elf- (or nios2-linux-gnu-)
$ make 3c120_defconfig
$ make
Now you will have u-boot-dtb.bin as final binary output. We will use this to program the flash.
Open yet another terminal to run gdb-server,
$ nios2-gdb-server --tcpport 2342 --tcppersist
Run gdb and download the binary to SDRAM at 0xd4000000,
$ nios2-elf-gdb
(gdb) target remote localhost:2342
(gdb) restore u-boot-dtb.bin binary 0xd4000000
(gdb) jump *0xd4000000
Open another terminal to connect the serial port,
$ nios2-terminal
Now press enter and you will see the u-boot prompt on the serial, erase and program the CFI flash at 0xe2800000,
==> erase e2800000 +80000
==> cp.b d4000000 e2800000 80000
If you want to change the serial device for console, you will need to select it with "$ make menuconfig" in u-boot dir.
Device Drivers ---> Serial drivers --->
[*] Require a serial port for console
[*] Enable Driver Model for serial drivers
[ ] Enable an early debug UART for debugging
[ ] Altera JTAG UART support
[*] Altera UART support
[ ] NS16550 UART or compatible
And change the "stdout-path=..." property with your serial path to the chosen node in dts, like this,
chosen {
stdout-path = &uart_0;
};
Follow u-boot/doc/README.nios2 to add a new board to u-boot.
You will need to select this feature in Linux kernel with "$ make menuconfig",
Processor type and features ---> [*] Passed kernel command line from u-boot
The device tree blob used in u-boot is exported as an environment variable ${fdtcontroladdr}. It can be used to boot Linux vmImage.
==> bootm ${loadaddr} - ${fdtcontroladdr}
U-Boot 2016.01-rc2-00169-g1c0e84c (Dec 19 2015 - 10:10:06 +0800)
CPU: Nios-II
DRAM: 128 MiB
Flash: 64 MiB
Model: Altera NiosII Max10
SYSID: facecafe, Sun Dec 13 02:52:00 2015
Net: eth0: ethernet@400
=> setenv ethaddr 00:07:ED:0A:03:29
=> setenv ipaddr 192.168.1.10
=> setenv serverip 192.168.1.5
=> saveenv
Saving Environment to Flash...
Un-Protected 1 sectors
Erasing Flash...Erased 1 sectors
Writing to Flash... done
Protected 1 sectors
baudrate=115200
ethaddr=00:07:ED:0A:03:29
fdtcontroladdr=cff4cb8c
ipaddr=192.168.1.10
loadaddr=0xcc000000
serverip=192.168.1.5
stderr=serial@18001600
stdin=serial@18001600
stdout=serial@18001600
ver=U-Boot 2016.01-rc2-00169-g1c0e84c (Dec 19 2015 - 10:10:06 +0800)
Environment size: 285/65532 bytes
=> bd
DRAM bank = 0x00000000
-> start = 0xC8000000
-> size = 0x08000000
flash start = 0xF4000000
flash size = 0x04000000
flash offset= 0x00000000
ethaddr = 00:07:ED:0A:03:29
ip_addr = 192.168.1.10
baudrate = 115200 bps
=> fl
Bank # 1: Altera QSPI flash Size: 64 MB in 1024 Sectors
F4000000 +4000000
=> cpu detail
-1: cpu@0 Nios-II
ID = 0, freq = 75 MHz: L1 cache, MMU
=> dm tree
Class Probed Name
----------------------------------------
root [ + ] root_driver
simple_bus [ + ] |-- sopc@0
serial [ + ] | |-- serial@18001600
mtd [ + ] | |-- quadspi@0x180014a0
misc [ + ] | |-- sysid@18001528
eth [ + ] | |-- ethernet@400
timer [ + ] | |-- timer@18001440
gpio [ ] | |-- gpio@180014d0
gpio [ ] | |-- gpio@180014c0
timer [ ] | `-- timer@880
simple_bus [ ] `-- cpus
cpu [ ] `-- cpu@0
=> gpio status -a
Bank led:
led0: unknown
led1: unknown
led2: unknown
led3: unknown
Bank button:
button0: unknown
button1: unknown
button2: unknown
=> gpio clear led0
gpio: pin led0 (gpio 0) value is 0
=> mii info
PHY 0x00: OUI = 0x5043, Model = 0x0C, Rev = 0x02, 1000baseT, FDX
PHY 0x01: OUI = 0x5043, Model = 0x0C, Rev = 0x02, 10baseT, HDX
=> mdio list
ethernet@400:
0 - Marvell 88E1111S <--> ethernet@400
=> ping 192.168.1.5
Using ethernet@400 device
host 192.168.1.5 is alive
All the devices you referred, must be properly virtual addressed. The cache bypassing macro, ldbio/stbio, may NOT be used for some drivers.
Kernel region, cached : only for sdram
(sdram | 0x0) for nommu, (sdram | 0xc0000000) for mmu.
IO region, uncached: all the others, including cfi flash, epcs/spi flash, uart, jtaguart, timer, lan, cf ,etc.
(port | 0x80000000) for nommu, (port | 0xe0000000) for mmu.
For exmaple, if the cfi flash is located at physical address 0x04000000, now you should refer to address 0x84000000 for nommu or 0xe4000000 for mmu. eg,
Community support is provided Monday to Friday. Other contact methods are available here.
Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.
For more complete information about compiler optimizations, see our Optimization Notice.