Design Example - Max10 10 DDR3 300MHz UniPHY Half Rate x24

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Design Example - Max10 10 DDR3 300MHz UniPHY Half Rate x24

Last Major Update

Initial Release – July 2015 – Max10 DDR3 SDRAM UniPHY 300MHz Half Rate, Quartus II v15.0, DDR3 SDRAM Controller with UniPHY.

Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to design a 24-bit wide, 300-MHz DDR3 SDRAM interface working with a Max10 FPGA development kit using a 24-bit wide DDR3 SDRAM interface comprises an IS43TR16640A-125JBLI and an IS43TR81280A-125JBLI DDR3 SDRAM components. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the UniPHY IP. The lab will not cover any of the steps in detail but simply show an overview of the design process.

The UniPHY IP also generates an example top level file, an example driver, and a test bench including an external memory model. All these will be used to demonstrate the DDR3 SDRAM functionality.

Design Specifications

The table below lists the specifications for this design:

Attribute	Specification
Quartus version	QuartusII v15.0
FPGA	10M50DAF484C6GES
Kit	Developement Kit
Memory device	DDR3 SDRAM (ISSI IS43TR16640A-125JBLI and ISSI IS43TR81280A -125JBLI)
Memory speed	800MHz
Memory topology	X24-bit, 2 DDR3 SDRAM components
IP used	DDR3 SDRAM Controller II with UniPHY IP and generated example top Quartus project

Lab Steps

The lab uses Quartus II v15.0 and has Modelsim set up for simulation. The lab assumes the reader is a competent user of these tools and many of their features.

A Quartus archive for the final project is also included for reference. Files for this lab are located in this zip file –  Max10_Uniphy_ddr3.zip. Create a new folder for the project and place the files in it.

Design Generation

1. In the Quartus II software, create a Quartus II project using the New Project Wizard available from the File menu. For this lab, use following information to setup the project accordingly: 

• Working directory : < your project folder >
• Project name : <variation_name>
• Device name : 10M50DAF484C6GES
• Leave other settings to default

2. Launch the IP Catalog from the Tools menu

3. Double click DDR3 SDRAM Controller with UniPHY IP from the Memory Interfaces and Controllers > Memory Interfaces with UniPHY folder in the Library list. 

• Pop up window will appears to let you choose the location to save this IP file. Please select the folder you created above. 
• You will be select your output file type on the If your license for ModelSim cannot support multiple HDL languages then choose verilog as output file type 
• Specify the Entity name and click OK

4. Set parameters for Memory Controller with UniHY

• PHY Settings Tab

1. Set Speed grade to 6.

2. Set Memory clock frequency to 300 MHz

3. Set PLL reference clock frequency to 100 MHz.

4. Select Half for half-rate Avalon-MM interface.

• Memory Parameters Tab

1. Select Discrete Device for Memory format.

2. Select 800 MHz for Memory device speed grade.

3. Type 24 for Total interface width.

4. Type 13 for Row address width.

5. Type 10 for Column address width.

6. Type 3 for Bank address width.

7. Select 5 for Memory CAS latency setting under Memory Initialization Options,

8. Select RZQ/4 for Output drive strength setting.

9. Select 5 for Memory write CAS latency setting.

10. Select Dynamic ODT off for Dynamic ODT(Rtt_WR) setting.

• Memory Parameters Tab

1. Set tIS (base) to 170ps

2. Set tIH (base) to 120ps

3. Set tDS(base) to 10ps

4. Set tDH(base) to 45ps

5. Set tDQSQ to 100ps

6. Set tDQSS to 0.27 cycles

7. Set tDSH to 0.18 cycles

8. Set tDSS to 0.18 cycles

9. Set tINIT to 500us

10. Set tMRD to 4cycles

11. Set tRAS to 35.0ns

12. Set tRCD to 13.75ns

13. Set tRP to 13.75ns

14. Set tREFI to 7.8us

15. Set tRFC to 110ns

16. Set tWTR to 6 cycles

17. Set tFAW to 30.0ns

• Board Settings Tab

1. Users should do board simulation for proper values in this page:

- In the Board Settings tab, set the slew rate parameters to the specified values below:

Select Use Altera’s default settings

CK/CK# slew rate (Differential): 2.0V/ps

Address and command slew rate: 1.0V/ns

DQS/DQS# slew rate (Differential): 2.0V/ns

DQ slew rate: 1.0V/ns

- Set the Intersymbol Interference/Crosstalk parameters to the specified value below:

Select Use Altera’s default settings

Address and command eye reduction (setup) = 0.0ns

Address and command eye reduction (hold) = 0.0ns

Write DQ eye reduction = 0.0ns

Write Delta DQS arrival time = 0.0ns

Read DQ eye reduction = 0.0ns

Read Delta DQS arrival time = 0.0ns

- Set the Board Skews parameters to the below value:

Maximum CK delay to DIMM/device : 0.2443ns

Maximum CK delay to DIMM/device : 0.21929ns

Minimum delay difference between CK and DQS : 0.02286ns

Maximum delay difference between CK and DQS : 0.04429ns

Minimum skew within DQS group : 0.01806ns

Minimum skew between DQS group : 0.04246ns

Average delay difference between DQ and DQS : -0.01152ns

Maximum skew within address and command bus: 0.07801ns

Average delay difference between address and command and CK: -0.04909ns

• Controller Settings Tab

- Set 64 for Maximum Avalon-MM burst length under Avalon Interface

5. Click on the Finish button and the pop-up window appear. Check the box for Generate Example Design and click on Generate.

6. Once the generation completed, click Exit.

Design Constraint, Compilation And Analysis

1. Set Top-Level Entity

The Megawizard generates a Quartus example top project. This project connects an example driver to the controller interface so users can quickly compile and test their UniPHY IP configuration on hardware.

• Open the example project located in <variation_name>_example_design/example_project. If the device you are using does not match the device in the example project, change the device in the project.

2. Perform Analysis and Synthesis 

This step is required so Quartus can determine the names of the external ports connected to the UniPHY for when the I/O assignments are created in the next step.

3. Assign the pin and DQ group settings 

Run the tcl script <variation_name>_pin_assignments.tcl to assign the pin and DQ group assignments. This tcl script is generated for you by the IP megawizard 

• Verify in the Assignment Editor that pin assignments have been created successfully 

4. Assign the pin locations

Pin locations for external memory systems are not automatically created. 

• Run the Max10_ddr3_pin_locations.tcl script to assign pin locations for the targeted kit 
• Verify in Pin Planner or Assignment Editor that pin locations have been created successfully

5. Do a Full Compile

• This should take about 10 minutes depending on the compiling PC.

Adding SignalTap file (Optional)

1. In the Quartus II software, launch SignalTap II Logic Analyzer from Tools menu.

• i. Under the Signal Configuration section, use the pll_ref_clk for the Clock
• ii. Include the following signals into your SignalTap file. Double click on the Setup area and search for the signals in the Named section on the pop-up window.

-ddr3_example_if0:if0|local_cal_fail

-ddr3_example_if0:if0|local_cal_success

-ddr3_example_if0:if0|local_init_done

-driver_avl_use_be_avl_use_burstbegin:traffic_generator_0|pass

-driver_avl_use_be_avl_use_burstbegin:traffic_generator_0|fail

-driver_avl_use_be_avl_use_burstbegin:traffic_generator_0|test_complete

-ddr3_example_if0_p0:p0|phy_cal_debug_info[31..0]

Design Analysis

1. Timing Analysis results 

'In the Compilation Report, Time Quest Timing Analyzer folder expand the three VT model folders, and the Report DDR folder

• Check the summary at the bottom of that report
• Check that all set up and hold timings pass

Note: there will be some unconstrained paths in the design. These are associated with the example driver that will not be part of a fully integrated HP controller design.

Design Hardware Test (Optional)

1. On board debug with Signal Tap 

Open the Signal Tap file and reset the .sof file to the one just created with the full compilation

• Program the kit FPGA with the .sof
• Run Signal Tap Analysis

- Reset the design by pushing the press button for CPU reset on the development kit

- Ensure that test complete goes high (signal tap is trigger on this), this is the end of the driver testing, check the driver's pass signal is high.

- Also check that calibration was successful and that the PLL is locked

- Also the LED1 on the board will light up and turn to green colour

Design Simulation(Optional)

The Quartus II software creates a complete design example for functional simulation in the <variation_name>_example_design/simulation/ directory. To run the RTL simulation, perform the following steps:

• Open the generated example project for the design example simulation, <variation_name>_example_design/simulation/<variation_name>_ example_sim.qpf.
• Select Tools -> Tcl Scripts... -> generate_sim_verilog_example_design.tcl and click "Run".
• Open Modelsim.
• Move into the directory ./verilog/mentor or ./vhdl/mentor.
• Start Modelsim and run the following commands
• Start Modelsim and run the "run.do" script: in Modelsim, enter "do run.do".
• The simulation will stop once the test complete signal goes high in the test bench
• CLICK “NO” WHEN ASKED IF YOU WANT TO FINISH, otherwise simulation will be reset
• Observe the results in the ModelSim Wave window

Notes/Comments

Update History

Initial Release – July 2015 – Max10 DDR3 SDRAM x24 300MHz, Quartus II v15.0, DDR3 SDRAM Controller with UniPHY, Max10 Development Kit.

See Also

1. List of designs using Altera External Memory IP 

External Links

1. Altera's External Memory Interface Solutions Center 

2. Altera's External Memory Interface Handbook 

Key Words

UniPHY, DDR3 SDRAM, Design Example, External Memory , Max 10