Design Example – Stratix 10 DDR3 SDRAM 400MHz Quarter Rate

Showing results for 
Search instead for 
Did you mean: 
363 Discussions

Design Example – Stratix 10 DDR3 SDRAM 400MHz Quarter Rate

Design Example – Stratix 10 DDR3 SDRAM 400MHz Quarter Rate

 Last Major Update

Initial Release – Dec 2017 – Stratix 10 DDR3 SDRAM 400MHz Quarter Rate x32, Quartus II v17.1, DDR3 SDRAM Controller, External Memory Interface Toolkit.

Design Overview

This design is meant as a demo style lab. It very briefly covers the steps required to design a 32-bit wide, 400-MHz DDR3 SDRAM interface working with a Stratix 10 FPGA using DDR3 SDRAM components with External Memory Interface Toolkit. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the Stratix 10 External Memory Interface IP. The lab will not cover any of the steps in detail but simply show an overview of the design process.

The Stratix 10 External Memory Interface IP also generates an example top level file, an example traffic generator, and a test bench including an external memory model. All these will be used to demonstrate the DDR3 SDRAM functionality.

Design Specifications

The table below lists the specifications for this design:

Quartus versionQuartusII v17.1
KitDevelopement Kit
Memory deviceDDR3 SDRAM (Micron MT41K512M16TNA)
Memory speed400MHz
Memory topologyx32-bit, 4 DDR3 SDRAM components 
IP usedDDR3 SDRAM Stratix 10 External Memory Interface IP and generated example top Quartus project


Lab Steps

The lab uses Quartus II v17.1 and has Modelsim set up for simulation. The lab assumes the reader is a competent user of these tools and many of their features.

The pinout file1 have been  pre-design for this lab to save time:

1. A pin location assignments TCL script ( S10_pin_assignment.tcl )

Create a new folder for the project and place the files in it.

Design Generation

1. In the Quartus II software, create a Quartus II project using the New Project Wizard available from the File menu. For this lab, use following information to setup the project accordingly: 

  • Working directory : <your project folder>
  • Project name : ddr3
  • Device name : 1SG280LU3F50I3VGS1
  • Leave other settings to default

2. Launch the IP Catalog from the Tools menu

3. Double click Stratix 10 External Memory Interfaces IP from the Memory Interfaces and Controllers folder in the Library list. IP Parameter Editor will be launch.

4. In New IP Variation window, specify the Entity name and click OK. For this lab, use following information to setup the IP variation accordingly. 

  • Entity name : ddr3
  • Leave other settings to default

5. In Presets window, select the preset matching or closest to the target memory device. 6. Specify the parameters on all tabs. The value should be based on the target memory device, FPGA device and board being used. For this lab, use following information to configure the remaining IP parameter that should be different than the default value or the preset. 

  • General tab
  • Clocks 
  • Uncheck the Use recommended PLL refeerence clock frequency checkbox
  • Select 133.333MHz for the PLL reference clock frequency
  • I/O tab (Uncheck the Use default I/O settings checkbox) 
  • PHY Inputs 
  • PLL reference clock I/O standard = LVDS (Based on Stratix 10 10SX115 Pin-out file)
  • Memory Topology tab 
  • Topology 
  • DQ width = 32
  • Mode Register Settings 
  • ODT Rtt nominal value = RZQ/6
  • Memory Timing tab 
  • tRRD = 7 cycles 
  • tFAW = 35.0 ns 
  • Board Timing tab (Based on internal board information) 
  • Slew Rates 
  • Use default slew rates = Checked
  • Intersymbol Interference/Crosstalk 
  • Board and Package Skews 
  • Package deskewed with board layout (DQS group) = Unchecked
  • Maximum board skew within DQS group = 0.02 ns
  • Package deskewed with board layout (address/command bus) = Checked
  • Maximum system skew within address/command bus = 0.02 ns
  • Average delay difference between DQS and CK = 0.02 ns
  • Maximum delay difference between DIMMs/devices = 0.05 ns
  • Maximum skew between DQS groups = 0.02 ns
  • Average delay difference between address/command and CK = 0.0 ns
  • Maximum CK delay to DIMM/device = 0.6 ns
  • Maximum DQS delay to DIMM/device = 0.6 ns
  • Diagnostics tab 
  • Calibration Debug Options 
  • Quartus II EMIF Debug Toolkit/On-chip Debug Port = Add EMIF Debug Interface 
  • Enabled Daisy-Chaining for Quartus II EMIF Debug Toolkit/On-Chip Debug Port = Unchecked 

Important Note : Review any warning messages displayed in the Messages Window and correct any errors before making further changes

Important Note : Instead of leaving it to default, ensure the parameters in Board Timing tab are configured correctly based on the actual target board as the value are vary from board to board. Use HyperLynx or similar simulator to obtain values of the actual target board.

Important Note : Take note on the info messages regarding which address/command pin placement scheme that need to follow based on the final IP setting. This info will be needed during pin assignment in the later stage.

Note : For Board and Package Skews, use Board Skew Parameter Tool available in Altera web to compute the value

Note : For detailed explanation of the parameters, refer to Parameterizing Memory Controllers with Stratix 10 External Memory Interface IP chapter of the External Memory Interface Handbook.

7. Click Example Design button at the top-right corner of the Parameter window, confirm the default path for the example design, and click OK.

8. Once the generation completed, click Close.

9. Click Finish. The configuration is saved as ddr3.qsys which located inside <your project folder> directory.

10. Since this lab will only use the example design files, click No when prompted to generate your IP.

11. In Integration with the Quartus II Software window, click Close.

12. Click Yes when prompted to add the Quartus II IP File to the project.

13. In terminal, change directory to <your project folder>/emif_0_example_design folder and run following commands in sequence: 

i. $ quartus_sh -t make_qii_design.tcl

ii. $ quartus_sh -t

Note :Review the readme.txt file generated under <your project folder>/emif_0_example_desig/qii/altera_emif_arch_nf_141/synth folder. The file contains high-level overview, recommendation and requirements of the IP based on the selected configuration.


Adding SignalTap file Into Existing Example Design (Optional)

1. In the Quartus II software, launch SignalTap II Logic Analyzer from Tools menu.

i. Under the Signal Configuration section, use the pll_ref_clk for the Clock

ii. Include the following signals into your SignalTap file. Double click on the Setup area and search for the signals in the Named section on the pop-up window.

  • emif_0_example_design|local_cal_fail
  • emif_0_example_design|local_cal_success
  • altera_emif_avl_tg_top:tg|traffic_gen_fail_0
  • altera_emif_avl_tg_top:tg|traffic_gen_pass_0
  • altera_emif_avl_tg_top:tg|traffic_gen_timeout_0


Design Constraint, Compilation And Analysis

1. In the Quartus II software, open the generated example design Quartus II project ( ed_synth.qpf) using the Open Project available from the File menu. The Quartus II project file should be under < your project folder >/emif_0_example_desig/qii folder.

2. Assign the location for all top level pins. Pin locations for external memory systems are not automatically created as it depend on the individual board layout and device package being used. For this lab, do the following steps: 

i. Place the S10_pin_assignment.tcl in < your project folder >/emif_0_example_desig/qii.

ii. Launch the Tcl Scripts from Tools menu.

iii. In the TCL Scripts window, select the S10_pin_assignment.tcl script under the Project folder in the Libraries and click Run to run the script.

iv. Click OK when a window appeared indicating the script has been executed and click Close to close the TCL Scripts window .

v. Verify in Pin Planner or Assignment Editor available under the Assignments menu to ensure the pin locations has been assigned correctly

Note: Board designer should comply with the following pin-out guideline when designing the board. To ensure the correctness, cross-check the pin location assignment with the respective document too. 

  • Guidelines for Stratix 10 External Memory Interface IP topic under Planning Pin and FPGA Resources chapter of the External Memory Interface Handbook.
  • Pin locations section in the readme.txt file generated under < your project folder >/emif_0_example_desig/qii/altera_emif_arch_nf_141/synth folder.
  • Stratix 10 Device Pin-Out Files on Altera web. 
  • Stratix 10 External Memory Interface Pin Information on Altera web. Use the address/command pin placement scheme information (as in noted in Design Generation stage) to determine which column should be referred to.

3. Run full compilation by clicking the Start Compilation under the Processing menu. The compilation may take around 10 minutes to complete depending on compilation PC.

4. Once the compilation complete, ensure that there are no timing violation. There are 2 areas that should be check as below: 

  • In Messages window, ensure that "Critical Warning (332148): Timing requirements not met" message has not being printed out.
  • In Compilation Report window, in emif_0_example_design table under each TimeQuest Timing Analyzer / < Operating condition > / Report DDR folder, ensure all number are positive. Note that this report only cover for those that are under Stratix 10 External Memory Interface IP clock domain.

5. Review all the Critical Warnings and Warnings and determines if it is acceptable or need to be address.


Design Hardware Test (Optional)

1. In the Quartus II software, launch SignalTap II Logic Analyzer from Tools menu.

2. In Jtag Chain Configuration window under SignalTap II Logic Analyzer GUI, configure the Hardware and Device based on the targeted board. For File, browse for the ed_synth.sof file and click Open.

3. Click Program Device button to configure the FPGA.

4. Select the SignalTap instance and click the Autorun Analysis button next to Instance Manager label. The SignalTap II Logic Analyzer Pane will shows the acquired data from each signal in the Data tab. At this stage, all signal will be low as the global_reset_n signal is still asserted.

5. In In-System Sources and Probes Editor Pane, click the source[0] instance value under the Data column to change it from 0 to 1. This will de-assert the global_reset_n signal in the hardware.

6. Now observe the data for local_cal_success and traffic_gen_pass and traffice_gen_timeout instances change from 0 to 1 on the SignalTap which indicate the calibration is success and pass the example driver tests.


External Memory Interface Toolkit Test (Optional)

1. To understand the calibration value of the design you can use the External Memory Interface Toolkit from Tools>System Debugging Tools menu.

2. Double click on the Initialize Connection button on the Tasks Pane.

3. Then double click on the Link Project to Device button. A pop-up window will appear with the information related to the design. Click the OK button on the pop-up window.

4. Finally, double click on the Create Memory Interface Connection button. Another pop-up window will appear to identified the connections. Click the OK button on the pop-up window.

5. Once the connection is established, scroll down the Tasks pane and look for the Generate All Reports button. Double click on it and the toolkit will generate the calibration report and summary report.

6. The reports will be available under the Report

See Also

List of designs using Altera External Memory IP

External Links

  1. Altera's External Memory Interface Solutions Center 
  2. Altera's External Memory Interface Handbook
Version history
Last update:
‎06-27-2019 05:14 PM
Updated by: