Initial Release – Dec 2017 – Stratix 10 DDR3 SDRAM 400MHz Quarter Rate x32, Quartus II v17.1, DDR3 SDRAM Controller, External Memory Interface Toolkit.
This design is meant as a demo style lab. It very briefly covers the steps required to design a 32-bit wide, 400-MHz DDR3 SDRAM interface working with a Stratix 10 FPGA using DDR3 SDRAM components with External Memory Interface Toolkit. The purpose of the lab is for the reader to get a basic feel for what steps are involved in getting an external memory working with an Altera FPGA and the Stratix 10 External Memory Interface IP. The lab will not cover any of the steps in detail but simply show an overview of the design process.
The Stratix 10 External Memory Interface IP also generates an example top level file, an example traffic generator, and a test bench including an external memory model. All these will be used to demonstrate the DDR3 SDRAM functionality.
The table below lists the specifications for this design:
|Quartus version||QuartusII v17.1|
|Memory device||DDR3 SDRAM (Micron MT41K512M16TNA)|
|Memory topology||x32-bit, 4 DDR3 SDRAM components|
|IP used||DDR3 SDRAM Stratix 10 External Memory Interface IP and generated example top Quartus project|
The lab uses Quartus II v17.1 and has Modelsim set up for simulation. The lab assumes the reader is a competent user of these tools and many of their features.
The pinout file1 have been pre-design for this lab to save time:
1. A pin location assignments TCL script ( S10_pin_assignment.tcl )
Create a new folder for the project and place the files in it.
1. In the Quartus II software, create a Quartus II project using the New Project Wizard available from the File menu. For this lab, use following information to setup the project accordingly:
2. Launch the IP Catalog from the Tools menu
3. Double click Stratix 10 External Memory Interfaces IP from the Memory Interfaces and Controllers folder in the Library list. IP Parameter Editor will be launch.
4. In New IP Variation window, specify the Entity name and click OK. For this lab, use following information to setup the IP variation accordingly.
5. In Presets window, select the preset matching or closest to the target memory device. 6. Specify the parameters on all tabs. The value should be based on the target memory device, FPGA device and board being used. For this lab, use following information to configure the remaining IP parameter that should be different than the default value or the preset.
Important Note : Review any warning messages displayed in the Messages Window and correct any errors before making further changes
Important Note : Instead of leaving it to default, ensure the parameters in Board Timing tab are configured correctly based on the actual target board as the value are vary from board to board. Use HyperLynx or similar simulator to obtain values of the actual target board.
Important Note : Take note on the info messages regarding which address/command pin placement scheme that need to follow based on the final IP setting. This info will be needed during pin assignment in the later stage.
Note : For Board and Package Skews, use Board Skew Parameter Tool available in Altera web to compute the value
Note : For detailed explanation of the parameters, refer to Parameterizing Memory Controllers with Stratix 10 External Memory Interface IP chapter of the External Memory Interface Handbook.
7. Click Example Design button at the top-right corner of the Parameter window, confirm the default path for the example design, and click OK.
8. Once the generation completed, click Close.
9. Click Finish. The configuration is saved as ddr3.qsys which located inside <your project folder> directory.
10. Since this lab will only use the example design files, click No when prompted to generate your IP.
11. In Integration with the Quartus II Software window, click Close.
12. Click Yes when prompted to add the Quartus II IP File to the project.
13. In terminal, change directory to <your project folder>/emif_0_example_design folder and run following commands in sequence:
i. $ quartus_sh -t make_qii_design.tcl
ii. $ quartus_sh -t make_sim_design.tc
Note :Review the readme.txt file generated under <your project folder>/emif_0_example_desig/qii/altera_emif_arch_nf_141/synth folder. The file contains high-level overview, recommendation and requirements of the IP based on the selected configuration.
1. In the Quartus II software, launch SignalTap II Logic Analyzer from Tools menu.
i. Under the Signal Configuration section, use the pll_ref_clk for the Clock
ii. Include the following signals into your SignalTap file. Double click on the Setup area and search for the signals in the Named section on the pop-up window.
1. In the Quartus II software, open the generated example design Quartus II project ( ed_synth.qpf) using the Open Project available from the File menu. The Quartus II project file should be under < your project folder >/emif_0_example_desig/qii folder.
2. Assign the location for all top level pins. Pin locations for external memory systems are not automatically created as it depend on the individual board layout and device package being used. For this lab, do the following steps:
i. Place the S10_pin_assignment.tcl in < your project folder >/emif_0_example_desig/qii.
ii. Launch the Tcl Scripts from Tools menu.
iii. In the TCL Scripts window, select the S10_pin_assignment.tcl script under the Project folder in the Libraries and click Run to run the script.
iv. Click OK when a window appeared indicating the script has been executed and click Close to close the TCL Scripts window .
v. Verify in Pin Planner or Assignment Editor available under the Assignments menu to ensure the pin locations has been assigned correctly
Note: Board designer should comply with the following pin-out guideline when designing the board. To ensure the correctness, cross-check the pin location assignment with the respective document too.
3. Run full compilation by clicking the Start Compilation under the Processing menu. The compilation may take around 10 minutes to complete depending on compilation PC.
4. Once the compilation complete, ensure that there are no timing violation. There are 2 areas that should be check as below:
5. Review all the Critical Warnings and Warnings and determines if it is acceptable or need to be address.
1. In the Quartus II software, launch SignalTap II Logic Analyzer from Tools menu.
2. In Jtag Chain Configuration window under SignalTap II Logic Analyzer GUI, configure the Hardware and Device based on the targeted board. For File, browse for the ed_synth.sof file and click Open.
3. Click Program Device button to configure the FPGA.
4. Select the SignalTap instance and click the Autorun Analysis button next to Instance Manager label. The SignalTap II Logic Analyzer Pane will shows the acquired data from each signal in the Data tab. At this stage, all signal will be low as the global_reset_n signal is still asserted.
5. In In-System Sources and Probes Editor Pane, click the source instance value under the Data column to change it from 0 to 1. This will de-assert the global_reset_n signal in the hardware.
6. Now observe the data for local_cal_success and traffic_gen_pass and traffice_gen_timeout instances change from 0 to 1 on the SignalTap which indicate the calibration is success and pass the example driver tests.
1. To understand the calibration value of the design you can use the External Memory Interface Toolkit from Tools>System Debugging Tools menu.
2. Double click on the Initialize Connection button on the Tasks Pane.
3. Then double click on the Link Project to Device button. A pop-up window will appear with the information related to the design. Click the OK button on the pop-up window.
4. Finally, double click on the Create Memory Interface Connection button. Another pop-up window will appear to identified the connections. Click the OK button on the pop-up window.
5. Once the connection is established, scroll down the Tasks pane and look for the Generate All Reports button. Double click on it and the toolkit will generate the calibration report and summary report.
6. The reports will be available under the Report.
Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.
Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.
For more complete information about compiler optimizations, see our Optimization Notice.