Device Configuration

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All support for Intel NUC 7 - 13 systems has transitioned to ASUS. Read latest update.

Device Configuration

Device Configuration



Altera offers several configuration schemes for configuring FPGAs. This page should give an overview of the configuration schemes, give hints when to use a specific scheme and how to implement a specific scheme.


General Schemes

The two general schemes Altera offers are the passive and the active configuration scheme. For the passive scheme the FPGA is configured by an external device. For the active scheme the FPGA configures itself according to the MSEL setting.

Passive schemes are used when you are using an external configuration device. This could be a microcontroller, ECPx-device or a Max II CPLD. There could be several reasons why you want to chose a passive configuration scheme:

  • Use less components: If you already have a microprocessor in your system you can use the microprocessor to configure the FPGA
  • More flexibility in device configuration: For example you could store several FPGA configuration and depending on the conditions you could load another FPGA configuration.
  • Failsafe: If you use a CPLD as configuration device you could implement a failsafe mechanism which loads a recovery firmware when the flashing of a new firmware fails.

Use an active configuration scheme in the following cases:

  • You want to use as little components as possible: Basically you only need an FPGA and a Flash memory for the active configuration.
  • You don't use a microcontroller
  • You don't need multiple configurations
  • You don't need a failsafe mechanism, e.g. because you will only flash the memory with a JTAG programmer

This should give you a hint if the active or passive configuration scheme will be better suited for you project.

There is a page which gives you an overview of the configuration modes supported by the different FPGAs: Device Configuration Schemes 

The Passive Parallel Synchronous and Passive Parallel Asynchronous don't seem to be used in newer devices. That was the reason why they are omitted in the list above.


Default Boot Addresses For Active Configuration Schemes

Default boot addresses for configuration schemes
Configuration Schem Address (byte mode) Address (word mode)
Active Serial (AS) x1    
Active Serial (AS) x4    
Active Parallel (AP) 0x20000 0x10000


Programming the Flash Memory

You can follow these steps if you store your FPGA configuration in flash device. Altera offers several software tools for creating flash images and programming them onto the Flash device. Depending on the system you are developing you have to take different approaches.

The Flash programming using the PFL function is pretty easy to use and is recommended to programm the FPGA bitstream into the Flash memory. If you're using a Nios II processor in your design have a look at [[1]] on how to program the Nios II software onto the Flash.


Use PFL To Program Flash


If your setup looks like this:

4/4a/PFL_Flash_programming.png ( PFL Flash programming.png - click here to view image )

you can use the PFL (Parallel Flash Loader) component to program the flash (Parallel Flash Loader handbook). You can either create your own PFL design or you can you use the Factory default PFL image provided by Altera. If you don't have any explicit reasons then stick to the Factory default PFL image.

Convert .sof To .pof Image


After you have synthesized your project you should have a .sof file with the bitstream for your FPGA. This bitstream has to be converted to a .pof file. For this select in Quartus II' -> File-> Convert Programming Files....

d/de/Convert_sof_to_pof.png ( Convert sof to pof.png - click here to view image )

You have to select the configuration device, the configuration mode and the output file name in this dialog. If you want to store several designs in you configuration device you can add up to eight sof pages. Depending on the configuration mode you need to select either Configuration Master or SOF Data and then add the generated .sof file. Only the passive and the active parallel modes are supported by this tool.

Create Quartus II Programmer Project And Program Flash


After you have created the .pof file you can create a new Quartus II Programmer project. For this start the programmer: Quartus II -> Tools -> Programmer. Delete all devices which already exist. Then add your FPGA: Edit -> Add Device... and select your device. Select the device and add your configuration device: Edit -> Attach Flash Device.... Select the configuration device and select Edit -> Change File and select your generated .pof file. When you select Program/Confgiure you will see that the software automatically adds a Factory default PFL image to your FPGA device.

f/f4/Quartus_ii_programmer_settings_factory_pfl.png ( Quartus ii programmer settings factory pfl.png - click here to view image )

Now you can program your device and your FPGA should boot from your configuration device after reset.


Use Nios II Processor To Program Flash

If you have a Nios II processor system and the Flash is accessible from the processor system you can use this approach to program the FPGA. You can either use the graphical front end Nios II Flash Programmer which is a front end for the command line tools, or you can use the command line tools directly. For the prerequisites in using the Nios II Flash Programmer have a look at Nios II Flash Programmer User Guide Table 1 - 1.

If you want to program the flash from the command line you have to do the following three steps

  • Convert the .sof and .elf to flash images
  • Download the NiosII processor design to the FPGA (.sof file)
  • Program the FPGA flash file and NiosII flash file to the flash


Example bash script for programming the flash memory:



# This script programs the flash


# generate flash files

sof2flash --input="./toplevel.sof" --output="./programming_files/fpga_configuration.flash" --verbose --activeparallel --offset=0x20000

elf2flash --input="./software/program/program.elf" --output="./programming_files/niosii_firmware.flash" --boot="${QUARTUS_ROOT_DIR}/nios2eds/components/altera_nios2/boot_loader_cfi.srec" --base=0x6000000 --end=0x67FFFFF --reset=0x6400000 --verbose


# download Nios II design

nios2-configure-sof "./toplevel_sammelplatine.sof"

# nios2-download "./software/adas1128/adas.elf" -g # download and start the software for the Nios II processor


# optional: erase the flash memory before programming

# nios2-flash-programmer --erase-all --base=0x6000000 --id=0xABBA --verbose


# program flash files

nios2-flash-programmer "./programming_files/fpga_configuration.flash" --base=0x6000000 --id=0xABBA --program --verbose

nios2-flash-programmer "./programming_files/niosii_firmware.flash" --base=0x6000000 --id=0xABBA --program --verbose



In this case the flash memory starts at address 0x6000000 of the Nios II system. The Nios II program code will be stored beginning at address 0x6400000 and the Nios II Reset vector is also set to this address. In this case the configuration mode selected for the FPGA was Active Parallel which has a default offset of 0x20000 (all addresses are binary addresses).

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Last update:
‎12-21-2022 03:18 PM
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