This page is dedicated to users that would like to better understand how to make ECO changes in Quartus’ Chip Planner and Resource Property Editor software. Many times after performing a long compilation, a user may want to make a small change without having to do a complete re-compile or without changing the RTL code. The intention of this example is to show a user how to make minor changes to I/O pad parameters like inverting the output signal, changing termination, or changing drive strength. This example will also show how to make a more complicated logic change within an ALM in the Stratix V fabric.
The design used for this example is a simple Stratix V design. The design was targeted towards the Stratix V GX or GS FPGA Development kit to verify the changes in hardware. However, this example does not require that you target the design to hardware. A user can simply go through the software flow.
Here is a link to the kit.
Stratix V GX/GS FPGA Development Kit
The following qar file contains the design example.
Many times after performing a long compilation, a user may want to make a small change without having to do a complete re-compile or without changing the RTL code. The intention of this example is to show a user how to make minor changes to I/O pad parameters like inverting the output signal, changing termination, or changing drive strength. This example will also show how to make a more complicated logic change within an ALM in the Stratix V fabric.
This example uses Quartus 15.1.
After downloading the design example and opening in Quartus, review the top level of the design.
The snippet of code that we will focus on is on line #93:
logic_out <= eco_reg2(1) AND eco_reg2(0);
Input ports eco_in(1:0) go to a debounce circuit which debounces the user pushbuttons on the Stratix V GX/GS FPGA development kit. Once debounced, the signals are registered in three stages, eco_reg0, eco_reg1, and eco_reg2. eco_reg2 then feeds eco_out which feeds an output port on the design that goes to LEDs on the development kit. The logic_out signal performs a basic logic function on the two bits of eco_reg2.
We will be first changing the polarity of the logic_out register, then we’ll make a logic change to change the “AND” function for logic_out to “OR”.
Here are the steps to go through the example and change the output polarity of the output signal logic_out.
For the logic change example, you will want to understand the equations that will be shown for each LUT
Here are the steps to go through the example and change the logic_out from an AND of the eco_reg2 bit 1 and eco_reg2 bit 0 to an OR.
Accept the changes shown which kick off the fitter in ECO mode. The design will be checked to make sure no rules were violated and then fit for the ECO change.
The example design contains Signal Tap which was used to verify the logic change. The design was also targeted towards a Stratix V GX/GS PCIe development kit. The output logic_out as well as the last stage of the eco_reg pipeline register were brought out to LEDs on the board to verify the ECO changes were made as expected.
The following sof files were downloaded to the Stratix V GX/GS PCIe development kit to verify the changes.
Zips of the sof files can be found here:
It is highly advised that you re-run all timing analysis after you have made an ECO change. Pay special attention to the specific things that were changed in the design to make sure the new routing or placement has not resulted in negative slack in all timing corners.
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