Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.

Showing results for

- Intel Community
- Intel Community Knowledge Base
- FPGAs and Programmable Solutions Knowledge Base
- FPGA Wiki
- FPLL Output Clock Frequency Calculator

- Article History
- Subscribe to RSS Feed
- Mark as New
- Mark as Read
- Bookmark
- Subscribe
- Email to a Friend
- Printer Friendly Page
- Report Inappropriate Content

FPLL Output Clock Frequency Calculator

This calculator allows you to compute exact output clock frequency of fPLL. Because fPLL IP Parameter Editor GUI tells only *rounded* frequency as "Actual frequency", you have to calculate exact frequency by yourself.

**Formula:** fout = fin ÷ 2 × (M + K ÷ 232) ÷ N ÷ C

**Download: **File:Fpll calc a10s10.zip

You can get M, N, C, and K (pll_dsm_fractional_division) values from the IP Parameter Editor GUI.

The phase frequency difference (PFD) clocks from the reference clock path and the feedback loop path should be the same frequency.

fPFD = fin ÷ N

= fvco ÷ 2 ÷ (M + K ÷ 232) --- (1)

The output clock frequency is:

fout = fvco ÷ 2 ÷ 2 ÷ C --- (2)

Convert (1) as below because the VCO frequency fvco is unknown and needs to be eliminated.

fvco = fin ÷ N × 2 × (M + K ÷ 232) --- (3)

Plug (3) in (2).

fout = fin ÷ N × 2 × (M + K ÷ 232) ÷ 2 ÷ 2 ÷ C

= fin ÷ N × (M + K ÷ 2 32) ÷ 2 ÷ C

Version history

For more complete information about compiler optimizations, see our Optimization Notice.