FPLL Output Clock Frequency Calculator
Introduction
This calculator allows you to compute exact output clock frequency of fPLL. Because fPLL IP Parameter Editor GUI tells only *rounded* frequency as "Actual frequency", you have to calculate exact frequency by yourself.
1/11/A10_fPLL_GUI.PNG ( A10 fPLL GUI.PNG - click here to view image )
For Arria 10 and Stratix 10 Devices
Formula: fout = fin ÷ 2 × (M + K ÷ 232) ÷ N ÷ C
Download: File:Fpll calc a10s10.zip
You can get M, N, C, and K (pll_dsm_fractional_division) values from the IP Parameter Editor GUI.
2/2e/A10_fPLL_AdvTab.PNG ( A10 fPLL AdvTab.PNG - click here to view image )
How to get the fomula E.g. Arria 10 fPLL
The phase frequency difference (PFD) clocks from the reference clock path and the feedback loop path should be the same frequency.
fPFD = fin ÷ N
= fvco ÷ 2 ÷ (M + K ÷ 232) --- (1)
The output clock frequency is:
fout = fvco ÷ 2 ÷ 2 ÷ C --- (2)
Convert (1) as below because the VCO frequency fvco is unknown and needs to be eliminated.
fvco = fin ÷ N × 2 × (M + K ÷ 232) --- (3)
Plug (3) in (2).
fout = fin ÷ N × 2 × (M + K ÷ 232) ÷ 2 ÷ 2 ÷ C
= fin ÷ N × (M + K ÷ 2 32) ÷ 2 ÷ C
