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# Introduction

This calculator allows you to compute exact output clock frequency of fPLL. Because fPLL IP Parameter Editor GUI tells only *rounded* frequency as "Actual frequency", you have to calculate exact frequency by yourself.

# 1/11/A10_fPLL_GUI.PNG ( A10 fPLL GUI.PNG - click here to view image )

## For Arria 10 and Stratix 10 Devices

Formula: fout = fin ÷ 2 × (M + K ÷ 232) ÷ N ÷ C

You can get M, N, C, and K (pll_dsm_fractional_division) values from the IP Parameter Editor GUI.

# f/f6/A10_fPLL_BlockDiagram.PNG ( A10 fPLL BlockDiagram.PNG - click here to view image )

The phase frequency difference (PFD) clocks from the reference clock path and the feedback loop path should be the same frequency.

fPFD = fin ÷ N

= fvco ÷ 2 ÷ (M + K ÷ 232) --- (1)

The output clock frequency is:

fout = fvco ÷ 2 ÷ 2 ÷ C --- (2)

Convert (1) as below because the VCO frequency fvco is unknown and needs to be eliminated.

fvco = fin ÷ N × 2 × (M + K ÷ 232) --- (3)

Plug (3) in (2).

fout = fin ÷ N × 2 × (M + K ÷ 232) ÷ 2 ÷ 2 ÷ C

= fin ÷ N × (M + K ÷ 2 32) ÷ 2 ÷ C

Version history
Revision #:
1 of 1
Last update:
‎06-26-2019 11:52 PM
Updated by:
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