Fault Tree Analysis (FTA) uses tree structures to decompose system level failures into combinations of lower-level events, and Boolean gates to model their interactions. The objective of this debug FTA example is to help troubleshoot and identify issue related to Altera JESD204B IP Core and resolve it effectively.
Synchronization request signal (SYNC_N) not de-asserted in JESD204B subsystem is a very common issue that user might encounter. The complexity of such issue's debugging are due to below factors:
i) Multiple possible root causes
ii) Difficult to isolate the problem to a specific area of the design and hardware setup.
iii) Requires significant effort and time to isolate the hypothesis.
Fault Tree Analysis Diagram & Table
The FTA example : FTA_JESD204B_sync_n_not_de-assert consists of a FTA diagram and table used to debug and root cause the SYNC_N signal not de-asserted issue happens in the JESD204B subsystem. In the FTA diagram, multiple hypothesis are made based on the failure symptom as described. For each of the hypothesis, it can have 2nd level or up to 3rd level suspects. The FTA diagram will then be converted into a table format to proper keep track of the debug progress. In the FTA table, for every suspect listed , it needs to have some action items to be performed to verify it together with some additional category information to be filled in such as Owner, Target completion date, status/Results, Possible Next Step and Priority level.