Flash Programmer

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Flash Programmer

During development, we use nios2-configure-sof and nios2-download to config the FPGA and run Nios II program from SDRAM. But the content of FPGA and SDRAM will lose when power off. To enable the system to start from power on, we need to write sof and program to flash. But flash have limited write life and the write speed is slow, so you should not program the flash until you have your system mostly tested.

Though we can use JTAG UART as console with nios2-terminal during development. You should not use it as console device if you want your system to start automatically when power on. Because the JTAG UART will hang without a nios2-terminal connected. You should use Serial UART with a RS232C cable instead. You can keep both the JTAG UART and serial UART in SOPC builder, but you must disable "Support for console on Altera JTAG UART" in kernel config and rebuild the kernel image. Please check LinuxConfig about how to select the other console device instead of JTAG UART. You have to test the new kernel image with nios2-download. Don't run nios2-terminal, use minicom on Linux or Hyper-terminal on Windows. Make sure it runs correctly over the RS-232C COM port.

Only after you have tested the program from sdram, you may try to write the flash. You will write the sof and program image seperately. You must find out what kind of flash you will use. There may be CFI flash, or EPCS flash, or both of them. <span id="fck_dom_range_temp_1285280942148_81" />

First, you must decide where to configure FPGA, from CFI or EPCS. This will mostly depend on the hardware, config mode pins or CPLD. You need to check the manual if it is a dev board. For DE2, DE1, some eval and starter boards, the sof is loaded in EPCS flash. For most other Altera dev boards, you can select one either CFI or EPCS with the CPLD. The CPLD will control the config offset on CFI, eg, 0xc00000.

Next, you must decide where to store the program. Most dev boards have a CFI flash, and you can use it by default. If your board have space on EPCS, you may use it but EPCS is usually slower than CFI during read. You must tell which component to use for reset vector, CFI flash or EPCS controller, in SOPC builder. If you change it, you regenerate the sof. You don't need to rebuild the kernel image.

The altera epcs boot loader is position independent. It is located in a onchip memory inside the epcs controller. The elf2flash gets load address from the elf.

The Altera flash conversion utility can add a Altera supplied boot loader, which will load the image to SDRAM and execute. The kernel image is compiled to start from SDRAM, (sdram base + boot link offset of the uncompress loader). So the start up procedures will be

1. power on reset
2. config sof from flash to FPGA
3. Nios II CPU start at the reset vector, which contain the boot loader
4. the boot loader copy program image from flash to SDRAM, at (sdram base + boot link offset) for our zImage
5. the uncompress loader in our zImage, copy the real kernel image to (sdram base)
6. kernel start up

Check your kernel dir, linux-2.6.x/include/nios2_system.h or check in SOPC builder , to find out the EPCS controller, or CFI flash 's base address. You will need these address value for flash programming.

You may find the boot loader sources at your altera suite installation, /opt/altera9.0/nios2eds/components/altera_nios2/boot_loader_sources

Some more details about EPCS boot loader, when you select reset vector to EPCS controller, a small hidden onchip memory is added by SOPC builder. The small onchip memory will have the Altera supplied boot loader for EPCS. So actually, it is "reset from onchip memory". (The real io port locates after this memory, it is at offset 0x200 currently. But if Altera change it on some devices someday, you will need to change it in EPCS driver.) Note, you must use Nios2 v5.1 sp1 or later to program the EPCS correctly.

The boot loader srec files is located in $SOPC_KIT_NIOS2/components/altera_nios2/

1. for cfi flash boot, use boot_loader_cfi.srec
2. for epcs boot on cyclone1,cyclone2, use boot_loader_epcs.srec 
3. for epcs boot on newer devices , use boot_loader_epcs_sii_siii_ciii.srec

If you use MMU, add --mmu option to nios2-flash-programmer command.

So we might have at least four alternatives,

1. sof in EPCS, program in CFI (default for DE2, DE1, some eval and starter boards)
2. sof in CFI, program in CFI
3. sof in EPCS, program in EPCS
4. sof in CFI, program in EPCS  ( in very rare case)

1. sof in EPCS, program in CFI

Using DE2_NET v1.5 as example (see TryOutuClinux ), find out and change the sof path, cfi base and epcs base below.

Open a Linux shell terminal, (or a Nios2 command shell on Windows)

# config the fpga

nios2-configure-sof ~/download/DE2_NET.sof

# change to your uClinux image dir

cd ~/uClinux-dist/images

# Creating .flash file for the FPGA configuration

sof2flash --epcs --input=~/download/DE2_NET.sof --output=standard.flash

# Programming flash with the FPGA configuration

nios2-flash-programmer --epcs --base=0x00680800 standard.flash

# Creating .flash file for the project

elf2flash --base=0x00000000 --end=0x3fffff --reset=0x0 --input=zImage --output=ext_flash.flash --boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srec

# Programming flash with the project

nios2-flash-programmer --base=0x00000000 ext_flash.flash

2. sof in CFI, program in CFI

Using Altera Nios Dev board, Cyclone II 2C35 , standard example, find out and change the sof path, and cfi base below.

# config the fpga

nios2-configure-sof $SOPC_KIT_NIOS2/examples/verilog/niosII_cycloneII_2c35/standard/standard.sof

# change to your uClinux image dir

cd ~/uClinux-dist/images

# Creating .flash file for the FPGA configuration

sof2flash --offset=0xC00000 --input=$SOPC_KIT_NIOS2/examples/verilog/niosII_cycloneII_2c35/standard/standard.sof --output=standard.flash

# Programming flash with the FPGA configuration

nios2-flash-programmer --base=0x00000000 standard.flash

# Creating .flash file for the project

elf2flash --base=0x00000000 --end=0xffffff --reset=0x0 --input=zImage --output=ext_flash.flash --boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_cfi.srec

# Programming flash with the project

nios2-flash-programmer --base=0x00000000 ext_flash.flash

3. sof in EPCS, program in EPCS

Using Altera Nios Dev board, Cyclone II 2C35 , standard example, find out and change the sof path, and epcs base below.

# config the fpga

nios2-configure-sof $SOPC_KIT_NIOS2/examples/verilog/niosII_cycloneII_2c35/standard/standard.sof

# change to your uClinux image dir

cd ~/uClinux-dist/images

# Creating .flash file for the FPGA configuration

sof2flash --epcs --input=$SOPC_KIT_NIOS2/examples/verilog/niosII_cycloneII_2c35/standard/standard.sof --output=standard.flash

# Programming flash with the FPGA configuration

nios2-flash-programmer --epcs --base=0x02200000 standard.flash

# Creating .flash file for the project

elf2flash --epcs --after=standard.flash --input=zImage --output=epcs_controller.flash --boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_epcs.srec

# Programming flash with the project

nios2-flash-programmer --epcs --base=0x02200000 epcs_controller.flash

MMU example

sof2flash --epcs --input=NiosII_cycloneII_2c35_full_featured.sof --output=fpga.flash

nios2-flash-programmer --epcs --mmu --base=0x03200000 fpga.flash

elf2flash --epcs --after=fpga.flash --input=zImage --output=zImage.flash --boot=$SOPC_KIT_NIOS2/components/altera_nios2/boot_loader_epcs.srec

nios2-flash-programmer --epcs --mmu --base=0x03200000 zImage.flash

Convert .flash file to binary, remote update

When we want to write FPGA config data, program image or file system image to CFI flash or EPCS on Nios2 uClinux, we need

1. create MTD device using MTD map driver and rebuild kernel, see following sections. eg, we have 3 mtd dev, with mtd 0,1 on CFI for jffs2,kernel and mtd 2 on EPCS for fpga config.
2. convert the .flash file (which is srec format), to binary format on Linux PC, eg. nios2-linux-uclibc-objcopy -I srec -O binary standard.flash standard.bin
3. find out the MTD devices on Nios2 uClinux, cat /proc/mtd
4. (transfer the file to Nios2..) write the binary file to MTD device on Nios2 uClinux, eg. copy config data to EPCS on mtd 2, 
5. cp standard.bin /dev/mtd2
6. sync # flush write cache to dev
7. Or you can use the flash utility included in uClinux-dist.

Note, you must use --epcs flag to sof2flash if and only if you want to generate for EPCS.

The EPCS config data is different from that of CFI flash.

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Convert elf object to binary,

nios2-elf-objcopy -O binary zImage zImage.bin

or,

nios2-linux-gnu-objcopy -O binary zImage zImage.bin

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You may try u_boot to program the flash. There is a C program to convert the rbf for EPCS flash in the wiki.