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New Release - June 12th 2017 - Quartus II v16.1 Installed
This design demonstrates:
a. The configuration of Frame Buffer II as frame reader only mode.
b. To show case the functionality of the Frame Reader only mode in simulation.
1. Create a Qsys system by using Frame Buffer II IP and configure it as Frame Reader only with 128x128 pixel.
2. Connect the Frame Buffer to an On-Chip Memory (128 bits of Avalon MM) that initialization by using smallAlt_128x6144.mif.
3. Three small 128x128 pixels frames stored in the onchip memory for simulation purpose.
4. Here is the frame size calculation: 128x128 Pixel * 2 color planes (parallel) * 8 color sample % 8 bit (one byte) = 32768 (0x8000)
5. The "Frame start address" of each of the small frame are, frame 0 = 0x0, frame 1 = 32'h8000 and frame 2 = 32'h10000
6. The irq signal of frame buffer will trigger when completed read a frame from memory.
7. Update the Frame start address register, the IP will start read the data from the memory that base on the address in the register.
8. Please download the design and refer to “frame_reader.qsys” for more information
1. Download the design -> File:Frame reader test.zip
2. Generate the Qsys and select “create simulation model” as Verilog.
3. Open modelsim and change the directory to …\Frame_reader_test\frame_reader\sim
4. Load the run_vsim.do
5. When the frame reader completed reading a frame, it will fire the irq signal
6. Please open the smallAlt_128x6144.mif, and you can compare the data with the “fr_out_data” port of frame reader.
For more complete information about compiler optimizations, see our Optimization Notice.