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The following patches improve the code generated by gcc. They will apply to the 9.0 and 9.1 releases from Altera.
This tells gcc that 'ld rn,0(rm)' and 'ld rn,constant(rm)' execute in the same time, and may save a register move.
When an aggregate data item is placed in the 'small data' area, eg by using __attribute__((section(".sdata"))), use %gprel(symbol+constant)(%gp) to access it instead of allocating another register (or sometimes 2 registers) to point to the structure.
Useful for small memory systems where the ldscript and memory map arrange for all the 'directly coupled' data memory to be accessed as offsets from %gp.
NB: The reversed checks are probably unnecessary, the gcc documentation imples that it always converts 'constant + symbol' to 'symbol + constant'.
Sometimes, but not always, a 'symbol + const' rtx is encapsulated inside a 'CONST' rtx.
Remove the encapsulation prior to perfroming the tests in patch 3.
Expand movsi for 32 bit constants into two rtx (instead of generating the instruction pair during code generation). Allows gcc to separate the instructions for scheduling purposes.
It will also allow further optimistaions that defer the addition of %lo() to a later ldw or stw instruction.
The wrong offset into the list of register names was used when the readra/readrb/writerc bits were clear.
Change i from unsigned long to int so that it matches the printf formats. Use a cast to int16_t (not two shifts by 16) to get a 16 bit value sign extended (now just assumes a 2s compliment host). (Needs patch 8.)
The mask used by the disassembler to detect break instructions was missing a bit - so illegal instruction encodings (those with 0x35 instead of 0x34) got decoded as break.
The trap instruction is documented as having an optional imm5 argument. Stop gas erroring if is it absent (uses same nasty hack as is used to detect the optional argument to break).
Change the definition of trap to include an imm5 value. Both gas and the disassembler now support it. (Apply patches 11 and 12 together.)
Collect2 creates one of its output files with a random mode.
Code size and 'register pressure' can be reduced by assigning addresses near 0 to data (or io) and then accessing it using signed 16bit offsets from r0.
This patch implements this in the linker.
If compiler generates a 'gp' relative address that is outside the addresses accessible from 'gp', but is accessible from 'r0' then the instruction is modified to use r0 instead gp and the absolute address inserted.
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For more complete information about compiler optimizations, see our Optimization Notice.