How can I avoid common mistakes when implementing Intel® FPGA configuration schemes?

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How can I avoid common mistakes when implementing Intel® FPGA configuration schemes?

All Intel FPGAs need to be configured with a user image to perform the desired user function.  

Depending on the device family, Intel FPGAs support different modes for configuration and have different architectures and requirements to facilitate successful configuration.

Since it is imperative to mitigate against configuration failures when designing the target board, this short document lists some of the mistakes that are commonly made when implementing a configuration scheme with Intel FPGAs, which may result in configuration failures.

Table of Content

Intel® Cyclone® 10 FPGA, Intel® Arria® 10, and earlier devices

• Incorrect or missing pull-up resistors on Open-Drain configuration pins
• Dedicated or dual-purpose configuration pins are inadvertently left unconnected
• Excessive load on CONF_DONE
• Circuitry or buffers placed between FPGA AS pins and QSPI devices

Intel® Stratix® 10 and Intel Agilex® device

• Missing clocks during configuration
• SDM_IO pin connections do not match the Intel® Quartus® software project
• nSTATUS is not monitored
• 3V Tiles unpowered
• Conflicting pull-up/downs on SDM_IO Pins.
• Mismatch between the Configuration Clock source setting & board connection
• Missing Reset Release IP in design
• Conflicting MSEL connections/Debug provisioning
• Incorrect PMBus settings or usage of unsupported Voltage Regulators

General (Applicable to all device families)

• Usage of unsupported 3rd party SPI/QSPI devices for Active Serial Configuration
• 10-Pin download cable header not connected correctly
• Excessive load or signal integrity issues on configuration interfaces/pins

Useful Reference

Notices & Disclaimers

Intel® Cyclone® 10 FPGA, Intel® Arria® 10, and earlier devices

Device families in this category employ a state-machine based architecture for configuration control and processing, with dedicated and dual-purpose configuration pins. Below is a list of common mistakes made with these device families that could result in configuration failure.

Incorrect or missing pull-up resistors on Open-Drain configuration pins

Intel provides recommended values for pull-up resistors for configuration pins based on device characterization, which should be adhered to. Some configuration pins (nSTATUS, CONF_DONE, INIT_DONE etc) are implemented as Open-Drain and thus a pull-up of 10-K Ohms is mandatory such that they can drive a logic high when released by the FPGA.

Dedicated or dual-purpose configuration pins are inadvertently left unconnected

Dual-purpose Configuration Pins that are enabled in the Intel® Quartus® Prime Software project should not be left N/C on the target device and board. For example, if INIT_DONE is enabled in the project and not pulled high on the board, the device may not enter user mode after configuration completes. Check your Intel Quartus Prime Software project settings file (.qsf) to determine which options have been enabled.

Excessive load on CONF_DONE

When using Active Serial configuration mode, configuration success may be sensitive to the rise time of CONF_DONE. To prevent this, excessive load should not be connected to this pin and if driving an LED, this should be done via a field-effect transistor (FET) or buffer.

See:

• Can loading on the CONF_DONE line result in configuration failure from my configuration device?
• Can I use a buffer that has a bus hold input circuit to monitor CONF_DONE?

Circuitry or buffers placed between FPGA AS pins and QSPI devices

It is generally not recommended to place voltage translators or buffers between QSPI devices and the FPGAs Active Serial pins, as this can present propagation delay induced timing issues which may lead to configuration failures. A direct point-to-point connection between devices is recommended.

Intel® Stratix® 10 and Intel Agilex® device

Devices in this category employ a Triple Redundant Processor-based architecture (SDM) for configuration control and processing with dedicated SDM I/O pins that function based on user-defined settings. Below is a list of common mistakes made with these device families that could result in configuration failure.

Missing clocks during configuration

For designs that use transceivers, HBM2, PCIe, eSRAM, or HPS EMIF, the reference clocks for these must be stable and free running before configuration to avoid configuration failures. If configuration with a simple design without such elements is successful, this is a good indication that a missing reference clock is causing configuration failure with the complete design.

• See Why does configuration of Intel® Stratix® 10 devices fail when PCIe, HPS EMIF, eSRAM or HBM2 IP is used in the Intel® Quartus® Prime Pro design?

SDM_IO pin connections do not match the Quartus software project

SDM_IO functionality depends upon the user defined settings in the Intel Quartus Prime project, under Device & Pin Options -> Configuration -> Configuration Pins. Make sure these settings correlate with your board level implementation.

nSTATUS is not monitored

It is recommended that the nSTATUS signal from the FPGA is monitored when controlling nCONFIG. This is to ensure a reconfiguration request is successful as nCONFIG must only change when it has the same value as nSTATUS.  

• See Is there a minimum specification for how long nCONFIG should be driven low for successful configuration when using Intel® Stratix® 10 and Intel® Agilex™ devices?

3V Tiles unpowered

For designs that use 3V I/O, since these are implemented on Transceiver Tiles, failure to power the respective transceiver tiles before configuration begins can result in configuration failure.

• See Why does Intel® Quartus® Programmer fail to configure Intel® Stratix® 10 devices when you are using 3V I/O pins?

Conflicting pull-up/downs on SDM_IO Pins.

It is important to note that whilst most SDM_IO pins are weakly pulled high internally, some are weakly pulled low.

Mismatch between Configuration Clock source setting & board connection

The source for the internal oscillator can be set in the Intel Quartus Prime project. If OSC_CLK_1 is selected as the source, ensure the frequency setting matches what is equipped on the board. Note that if using Transceivers, a connection on OSC_CLK_1 is mandatory as this clock is used for Transceiver  calibration.

See:

• Why do ASx4 configuration fail when using OSC_CLK_1 as clock source?
• Can I use the Internal Oscillator setting of the Configuration Clock Source field for transceiver calibration on Intel® Stratix® 10 L-Tile and H-Tile devices?

Missing Reset Release IP in design

To ensure successful entry into user mode, it is recommended to instance the Reset Release IP in your design to hold user logic in reset until device configuration & initialization is complete.

Conflicting MSEL connections/Debug provisioning

Since MSEL pins may drive out during power-up, Intel recommends only connecting 4.7-kΩ pull-up or pull-down resistor to these pins and not driving them with active logic. It is also recommended to provision for the MSEL pins to be configured in JTAG mode, for debug purposes.

Incorrect PMBus settings or usage of unsupported Voltage Regulators

When using SmartVID enabled devices, ensure the Intel Quartus Prime project settings correctly reflect the voltage regulator that is being used and also that the Voltage Regulator uses a supported voltage output format as described in the Power Management User Guide for your chosen device.

See:

• Is the PWRMGT_ALERT signal generated by Intel Stratix 10 devices active high or active low?
• Are the Intel® Stratix® 10 device SDM_IO pins configured as open drain when used as PWRMGT_SDA and PWRMGT_SCL for SmartVID PMBus Power Management?
• Why do I need to ensure that all Stratix10 SmartVID devices use a PMBus voltage regulator?

General (Applicable to all device families)

Usage of unsupported 3rd party SPI/QSPI devices for Active Serial Configuration

Where possible, Intel recommends using one of the supported 3^rd party QSPI flash devices for Active Serial configuration.

• See Intel® Supported Configuration Devices

10-Pin download cable header not connected correctly

The 10-pin download cable has a specific pin-out for Intel download cable headers, and this should be followed to ensure compatibility with these cables.

Excessive load or signal integrity issues on configuration interfaces/pins

Intel recommend simulating configuration topologies with IBIS models to verify signal integrity.

If multiple devices are connected together in a JTAG chain, follow the buffering guidance in the following link:

• When should I buffer or terminate signals on a Joint Test Action Group (JTAG) chain?

 

Useful Reference

Device Configuration - Support Center

Notices & Disclaimers 

Intel technologies may require enabled hardware, software or service activation. 

No product or component can be absolutely secure.  

Your costs and results may vary.  

Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.

The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications.  Current characterized errata are available on request.

The Intel logo, and Intel Agilex are trademarks of Intel Corporation or its subsidiaries

2021-06-23

Parmindar Guraya