How do I generate gate-level simulation netlists

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How do I generate gate-level simulation netlists

How do I generate gate-level simulation netlists for sub-modules in my design and test for sensitivity to register power-up values?


1) Apply a design partition assignment on the appropriate level of hierarchy.


To enable the generation of a gate-level simulation netlist for a sub-block within the context of a top-level project (EG a specific lower-level IP) then a design partition assignment needs to be created for the sub-block instantiation.

The syntax for the design partition assignment is shown below

set_instance_assignment -name PARTITION <partition name> -to <instance of IP> -entity <top-level entity>

The easiest way to create the assignment is to perform the following steps in the Intel® Quartus® Prime Software GUI:

a) Synthesize the top-level project in the Intel® Quartus® Prime Software GUI.

b) Use the Project Navigator to locate the level of hierarchy that instantiates the IP sub-block for which the gate-level simulation netlist is required.

c) Right-click on the sub-block instance and select “Design Partition > Type = Default” as shown below:



a. This will then generate the appropriate constraint in the <project>.qsf file:

set_instance_assignment -name PARTITION sub_block -to U1 -entity Project_Top


2) Apply appropriate simulator settings in the EDA Tool Settings page.


Go to the Assignments > Settings > EDA Tool Settings>Simulation page and apply the appropriate simulator settings.




And “More EDA Netlist Writer Settings”=>



Which will write the following assignments into the <project>.qsf file:

set_global_assignment -name EDA_SIMULATION_TOOL VCS
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_FORCE_GATE_LEVEL_REG_INIT_X ON -section_id eda_simulation

The “EDA_FORCE_GATE_LEVEL_REG_INIT_X” assignment will initialize all registers in the design to “X”. If the registers have a sufficient reset, then they will be cleared through the assertion of the design reset. If they don’t then they will remain as “X” which will then propagate through the design during simulation.


3) Perform a full compilation of the design.


Full compilation will provide the ability to generate a simulation netlist for all stages (snapshots) of the compilation (synthesized, planned, placed, routed, retimed, final)

synthesized : synthesis netlist. No placement has taken place at this stage.

planned : Netlist after IO placement. No core logic has placed at this stage.

placed : Netlist after full placement. Placement has occurred but no routing or retiming into Hyper registers has taken place at this stage. Simulation netlist will contain all netlist optimizations that occurred during placement.

routed : Netlist after router stage. Full placement and routing has taken place however retiming of registers into Hyper register locations has not taken place yet. Simulation netlist will contain all netlist optimizations that occurred during placement and routing.

retimed : Netlist after retime stage. Full placement, routing and retiming has taken place including retiming of registers into Hyper register locations. Simulation netlist will contain all netlist optimizations including hyper retiming that occurred during placement, routing & retiming.

final : Netlist after final stage. Simulation netlist will contain all optimizations that occurred in any of the previous compilation steps. Main difference between this and the retimed netlist is that certain Hyper register locations can change due to hold time optimization.


4) Generate the Gate-Level simulation netlist using the “quartus_eda” command.


Run the following command to generate the appropriate gate-level simulation netlist:

quartus_eda --simulation <project name> --snapshot=<snapshot> --partition=<partition name>


quartus_eda --simulation Project_Top --snapshot=synthesized --partition=my_partition


quartus_eda --simulation Project_Top --snapshot=final --partition=my_partition

These commands will write out the simulation netlist (.vo or .vho) in the location specified in the “output directory” EDA Tool setting which defaults to “simulation/<simulator>” (See EDA Tool Settings).


5) Modify your testbench to account for any port list changes.


The majority of the sub-block port list will be identical between the original RTL and the generated gate-level simulation netlist however there may be some constructs such as generics that get evaluated/removed and are not passed down through the gate-level port list.

For this reason, you need to ensure that the parameterization of the sub-block IP within the context of the top-level design is the same as expected in your gate-level simulation as no generics/parameters can be changed within the netlist.

For example, take the following sub-block RTL code which contains a “dwidth” generic (with the generic being set to 16 from the top-level file):



This gets converted into the following port list within the generated gate-level simulation netlist:



“dwidth” gets evaluated to a constant (16) in the netlist.

As shown above, all sub-block parameterization gets evaluated within the gate-level netlist.

If the sub-block in question contains parameterization (such as generics) then you may need to modify your testbench to account for this.


6) Location of simulation models.


All simulation models are located under <Quartus installation directory>/eda/sim_lib

Although others may be required, the main models typically required for core level simulations are:

<Quartus installation directory>/eda/sim_lib/

<Quartus installation directory>/eda/sim_lib/

<Quartus installation directory>/eda/sim_lib/<simulator>


7) Simulate the gate-level netlist to see if the design is sensitive to the registers initializing to “X”


If you already have an RTL simulation setup, simply replace the RTL for the module in question with the gate-level simulation netlist.

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Your costs and results may vary.

Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.

The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.


Terrance Haughan



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Last update:
‎06-09-2021 06:24 PM
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