Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel Agilex® devices

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Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel Agilex® devices

The design demonstrates Ethernet operation between the Triple-Speed Ethernet Intel® FPGA IP core and onboard Marvell 88E1111 PHY chip through SGMII. TCL scripts are included to allow users to test the auto-negotiation feature,  internal MAC loopback, internal PHY loopback, and TX/RX interop with the external tester at a data rate of 10/100/1000 Mbps. The packet statistics report will be generated as the output result of the internal loopback test.

 

The design example can be found on the Intel® FPGA Design Store at https://www.intel.com/content/www/us/en/design-example/714770/intel-agilex-7-fpga-triple-speed-ethernet-and-on-board-phy-chip-reference-design.html.

 

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Last update:
‎03-14-2023 11:05 AM
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