The design demonstrates Ethernet operation between the Triple-Speed Ethernet Intel® FPGA IP core and onboard Marvell 88E1111 PHY chip through SGMII. TCL scripts are included to allow users to test the auto-negotiation feature, internal MAC loopback, internal PHY loopback, and TX/RX interop with the external tester at a data rate of 10/100/1000 Mbps. The packet statistics report will be generated as the output result of the internal loopback test.
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