Intel Generic Flash Controller Erase and Block Protect

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Intel Generic Flash Controller Erase and Block Protect


This wiki page is dedicated towards users that are using the Intel Generic Serial Flash controller with EPCQ flash or other flash and are looking to erase the entire flash and protect blocks of memory. There are some example designs, but none seemed to adequately cover erasing parts of the flash or the entire flash. Similarly, no examples were found to do block protection or protect the entire flash.

This example was created using Cyclone V, EPCQ256, and the Intel Generic Serial Flash controller. The example was compiled and programmed to a TerASIC Cyclone V development kit and then proven using System Console. The example should allow for embedded developers to leverage the sequence of read and write commands using system console into their NIOSII or other CPU complex.

Design Example

The following qar file contains the design example which was compiled and archived using Quartus version 18.1 build 625.

Intel Generic Flash Erase Protect.qar - see attached at the bottom of this article 

The example design contains a Platform Designer (Qsys) design that looks as follows:


The design uses a known good external clock running at 50Mhz on the TerASIC Cyclone V board at PIN_R20.

Hardware Used

This example runs on the TerasIC Cyclone V GX Starter board.

TerasIC Cyclone V-GX Starter Kit

Tcl Script

The following Tcl script is used to setup a number of procedures that can be run real time in System Console or be used as procedures for embedding into other scripts if needed.

System Console EPCQ256 Generic Flash IP.tcl

Running the Example

Using the procedures in Tcl script, the following can be performed:

  • Erase the entire contents of the EPCQ256.
  • Erase sectors of the EPC256 (sectors 0 through 511)
  • Write to memory locations
  • Read from memory locations
  • Protect all blocks of memory
  • Unprotect all block of memory

Program the Cyclone V and then open up System Console.

Once in System Console:

  • source System_Console_EPCQ256_Generic_Flash_IP.tcl

Now all the procedures are available to run.

Do the following:

  • Initial memory read: read_mem_test
  • Write memory test: write_mem_test
  • Erase sector 0: erase_sector 0
  • Erase sector 1: erase_sector 1
  • Erase sector 255: erase_sector 255
  • Erase sector 511: erase_sector 511
  • Memory read: read_mem_test
  • Bulk erase: erase_bulk

Will take a few minutes… should see “……” in blocks of 60 and then newline.

  • Memory read: read_mem_test
  • Protect all blocks from being written: block_protect
  • Read status register: read_status_reg

At any time, you can issue this command to check the status register of the Flash:

  • Attempt to write memory: write_mem_test
  • Memory read: read_mem_test

No memory should have been written

  • Unprotect all blocks: block_unprotect
  • Read status register: read_status_reg
  • Memory read: read_mem_test
  • Write memory: write_mem_test
  • Memory read: read_mem_test

The example provided works for Cyclone V and the EPCQ256. The example can be leveraged into other Intel FPGA families and other flash devices.


Update 2/6/20

  • The tcl script has been updated to support the following:
    • fast_read_memory procedures in serial, dual, and quad modes. 
    • fast_write_memory procedures in serial and quad modes.
    • Baud rate div/2
  • A document has been attached showing the timing for serial and quad read and writes used during debug at the IO interface level using Signal Tap.
Version history
Last update:
‎12-27-2022 01:35 PM
Updated by: