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Interlaken MegaCore Debug Checklist

Interlaken MegaCore Debug Checklist



0 Monitor these signals

nodesampling clock
srst_tx_commonclk_tx_common
srst_rx_commonclk_rx_common
tx_usr_srsttx_usr_clk
itx_ifc_errtx_usr_clk
itx_hungrytx_usr_clk
itx_overflowtx_usr_clk
itx_underflowtx_usr_clk
tx_lanes_alignedtx_usr_clk
burst_max_intx_usr_clk
burst_short_intx_usr_clk
burst_min_intx_usr_clk
rx_usr_srstrx_usr_clk
sync_lockedrx_usr_clk
word_lockedrx_usr_clk
rx_lanes_alignedrx_usr_clk
crc24_errrx_usr_clk
crc32_errrx_usr_clk
irx_overflowrx_usr_clk
rdc_overflowrx_usr_clk
rg_overflowrx_usr_clk
rxfifo_fill_levelrx_usr_clk
/ilk_core/hah/gx/pll_lockedmm_clk
/ilk_core/hah/gx/rx_is_lockedtodatamm_clk


1 Unable to acquire Word Lock/Sync on all lanes

Confirmed by failure of "word_locked" and "sync_locked" going high.

Link partner is not enabled

Incorrect reference clock frequency

The reference clock frequency should match the selection in the MegaWizard GUI.

Incorrect IO Buffer Type on reference clock or serial data lines

Make sure the receive buffer type matches the transmitter, typically PCML

For the clock, make sure buffer type matches clock buffer type, typically LVDS

Incorrect Pin Assignment on reference clock

Check the pin assignment used the .qsf file. Confirm the assignment matches your board schematic.

Incorrect IO Termination on reference clock or serial data lines

If the serial lines are not terminated on the board, make sure that you select On Chip Termination (OCT).

Incorrect Voltage supply to transceiver channels, VCCH

Check the Altera device family being used and supply the correct VCCH voltage. Stratix IV families will use either 1.4 or 1.5 V. The Stratix V family requires a 1.5 V source.

Inadequate VOD or Pre Emphasis settings at source

Before you proceed to tune the analog settings, try a serial loopback test. Program the Altera transceivers in serial loopback mode. In this mode the tx serial line is diverted back to the rx serial line for each channel. If the Interlaken core is able to acquire word lock and word sync in this mode, you will have to tune the transceiver analog settings to achieve word lock and word sync in normal operation.

If link partner is Altera FPGA, use Transceiver Toolkit to tune the transceiver analog settings or use the Reconfiguration Controller to change VOD and Pre-Emphasis values.

If link partner is not Altera FPGA, find the vendor's recommended method for tuning the tx analog values.

Inadequate Rx Equalization

Use the Transceiver Toolkit to tune the transceiver analog settings or use the Reconfiguration Controller to adjust the RX Equalization value.

Excessive jitter on reference clock

Check the jitter on the transceiver reference clock. Make sure the jitter is within the specifications

2 Unable to acquire lane alignment

Confirmed by "rx_lanes_aligned" staying deasserted, low.

Excessive lane-to-lane skew due to board design

Confirm that the board traces are length matched to meet the lane-to-lane skew specifications.

Excessive reference clock jitter, link partner

Check the jitter on the link partner's reference clock. Make sure it is within the specifications.

Excessive reference clock jitter

Check the jitter on the transceiver reference clock. Make sure the jitter is within the specifications

Receive datapath not reset correctly

Try toggling the reset of the Interlaken core. If toggling the reset achieves lane alignment, check for removal or recovery timing violations. Also, make sure that the design is appropriately constrained for all timing specifications. Make sure that you are using a Quartus II ACDS version in which the timing models are final for the part that your design is targetting.

3 Unable to acquire Frequency Lock on all lanes 

Confirmed by "rx_is_lockedtodata" not being all ones.

Incorrect reference clock frequency

The reference clock frequency should match the selection in the MegaWizard GUI.

Incorrect IO Buffer Type, reference clock and serial data lines

Make sure the receive buffer type matches the transmitter, typically PCML

For the clock, make sure buffer type matches clock buffer type, typically LVDS

Incorrect Pin Assignment, clock

Check the pin assignment used the .qsf file. Confirm the assignment matches your board schematic.

Incorrect IO Termination, reference clock and serial data lines

If the serial lines are not terminated on the board, make sure that you select On Chip Termination (OCT).

Incorrect Voltage supply to transceiver channels, VCCH

Check the Altera device family being used and supply the correct VCCH voltage. Stratix IV families will use either 1.4 or 1.5 V. The Stratix V family requires a 1.5 V source.

Excessive reference clock jitter

Check the jitter on the transceiver reference clock. Make sure the jitter is within the specifications

Inadequate VOD settings at source

Before you proceed to tune the analog settings, try a serial loopback test. Program the Altera transceivers in serial loopback mode. In this mode the tx serial line is diverted back to the rx serial line for each channel. If the Interlaken core is able to acquire word lock and word sync in this mode, you will have to tune the transceiver analog settings to achieve word lock and word sync in normal operation.

If link partner is Altera FPGA, use Transceiver Toolkit to tune the transceiver analog settings or use the Reconfiguration Controller to change VOD and Pre-Emphasis values.

If link partner is not Altera FPGA, find the vendor's recommended method for tuning the tx analog values.

Inadequate Pre-Emphasis at source

Use the Transceiver Toolkit to tune the transceiver analog settings or use the Reconfiguration Controller to adjust the RX Equalization value.

Inadequate Rx Equalization

Check the jitter on the transceiver reference clock. Make sure the jitter is within the specifications

4 Detecting CRC32 Errors

Unmatched MetaFrame Length

Make sure that the MetaFrame length is matched between the two link partners.

Incorrect reference clock frequency

The reference clock frequency should match the selection in the MegaWizard GUI.

Inadequate VOD settings at source

Before you proceed to tune the analog settings, try a serial loopback test. Program the Altera transceivers in serial loopback mode. In this mode the tx serial line is diverted back to the rx serial line for each channel. If the Interlaken core is able to acquire word lock and word sync in this mode, you will have to tune the transceiver analog settings to achieve word lock and word sync in normal operation.

If link partner is Altera FPGA, use Transceiver Toolkit to tune the transceiver analog settings or use the Reconfiguration Controller to change VOD and Pre-Emphasis values.

If link partner is not Altera FPGA, find the vendor's recommended method for tuning the tx analog values.

Inadequate Pre-Emphasis at source

Use the Transceiver Toolkit to tune the transceiver analog settings or use the Reconfiguration Controller to adjust the RX Equalization value.

Inadequate Rx Equalization

Check the jitter on the transceiver reference clock. Make sure the jitter is within the specifications

Timing violations

Confirm that your design meets all timing requirements. Make sure that you have correctly constrained all clocks and paths.

5 Detecting CRC24 Errors

Unmatched BURST_MAX setting

Confirm matching values for BURST_MAX between the two link partners

Unmatched BURST_MIN setting

Confirm matching values for BURST_MIN between the two link partners

Unmatched BURST_SHORT setting

Confirm matching values for BURST_SHORT between the two link partners

Incorrect frequency of rx user clock

Make sure that the frequency of the rx_usr_clk signal follows the values recommended in the Interlaken User Guide.

Receive lanes are reversed

It is easy to make the mistake of reversing the lane order between the link partners. The Interlaken MegaCore offers a parameter to reverse the lanes. Please see the Interlaken User Guide for instructions on how to reverse the lane order.

Timing violations

Fix any timing violations reported by TimeQuest during design compilation. Make sure that the design is correctly constrained for all clocks and datapaths.

6 Link Partner is detecting CRC32 Errors

Unmatched data rates

Make sure that the link partners are programmed for matching data rates. Check the frequency of link partners reference clocks.

Inadequate Tx Pre Emphasis

Perform a serial loopback test. If the test is successfully, then the issue could be due to inadequate Pre-Emphasis of the transmitters. Boost the Pre-Emphasis of the transmitters.

Incorrect reference clock frequency

Confirm that the frequency of the reference clock is the value selected in the MegaWizard GUI.

transmit datapath not reset correctly

Toggle the Interlaken core reset. If the reset causes the link partner to stop detecting CRC32 errors, then the issue is related to the resetting of the tx data path.

Incorrect output buffer type

Make sure the receive buffer type matches the transmitter, typically PCML

For the clock, make sure buffer type matches clock buffer type, typically LVDS

Incorrect VCCH voltage

Check the Altera device family being used and supply the correct VCCH voltage. Stratix IV families will use either 1.4 or 1.5 V. The Stratix V family requires a 1.5 V source.

Unmatched MetaFrame Length

Make sure that the MetaFrame length is matched between the two link partners.

7 Link Partner is detecting CRC24 Errors

Unmatched BURST_MAX setting

Confirm matching values for BURST_MAX between the two link partners

Unmatched BURST_MIN setting

Confirm matching values for BURST_MIN between the two link partners

Unmatched BURST_SHORT setting

Confirm matching values for BURST_SHORT between the two link partners

Transmitting Packet Mode vs Interleaved Mode

Make sure that the link partner can accept packets which is transmitted in either Packet Mode or Interleaved Mode.

Incorrect use of itx_sob and itx_eob user inputs

If the Interlaken core was generated with Interleave mode, make sure that the user logic is correctly drivning the itx_sob and itx_eob signals.

Incorrect frequency on usr_tx_clk

Make sure the frequency of the tx_user_clk signal is being clocked at the recommended frequency as specified in the Interlaken User Guide

user tx logic not honoring the itx_ready signal

If your application logic is not honoring the itx_ready, packets and/or bursts can get corrupted, causing CRC24 errors detected by the link partner.

Transmitter lanes are reversed

Try swapping the order of the transmit lanes. This can be done by changing the value of the hidden parameter, TX_SWAP_LANES. Please the Interlaken User Guide for details.

8 Link Partner is unable to perform Lane Alignment

Excessive jitter on reference clock

Check the jitter on the reference clock and confirm that it is to specification.

Timing violations/issues on TX MAC to PCS interface

Confirm that there are no timing violatins being reported by TimeQuest.

Confirm that timing constraints are being applied correctly for all clocks and datapath.

Confirm that the timing models are final for the device that you are tagetting.

Faulty reset sequence

Toggle the Interlaken core reset. If the reset causes the link partner to stop detecting CRC24 errors, then the issue is related to the resetting of the tx data path.

lane-to-lane skew out of specification

Check the board layout and confirm that the board traces for the Interlaken interface are matched.

9 Corrupted packets or segments detected at RX user interface

Incorrect frquency on irx_usr_clock

Confirm that the frequency of irx_usr_clk clock is within the requirements as described in the Interlaken User Guide.

Too shallow receive reassembly FIFO for bursty traffic

If the link partner can cause short bursts which can go over the line rate, you may want to increase the depth of the RX Reassembly FIFO. This can be done by changing the value of the hidden parameter,RXFIFO_ADDR_WIDTH.

timing violations

Confirm that there are no timing violatins being reported by TimeQuest.

Confirm that timing constraints are being applied correctly for all clocks and datapath.

Confirm that the timing models are final for the device that you are tagetting.

10 Link partner is not sending any packets

itx_calendar port is setting XOFF to all channels.

Check the value of the itx_calendar port. Make sure that you are not tukrning off any of the channels.

Link partner is not enabled

Make sure that the link partner's transmitters are enabled.

11 Link partner is not receiving any packets

Incorrect channel configuration

Check the itx_channel value at the itx user interface. If the link partner is configured to receive traffic only on a specific channel and you are transmitting to other than that channel, the the link parter will not be honoring the packets.

12 Poor TX performance, throughput is lower than expected

Inadequate frequency on itx_usr_clock

Check the frequency of the tx_usr_clk. Confirm that it is being toggled at the recommended frequency for your application. See the Interlaken User Guide for detais.

Link partner does not have all channels enabled

If sending packets to multiple channels, confirm that the link partner is programmed to receive packets from all expected channels.

13 Poor RX performance, throughtput is lower than expected

Inadequate frequency on irx_usr_clock

Check the frequency of the rx_usr_clk. Confirm that it is being toggled at the recommended frequency for your application. See the Interlaken User Guide for detais.

Inadvertent in-band flow control for some channels

Confirm that you are not XOFFing any of the channels at the itx_calendar port.

14 Unable to read or write any of the Interlaken IP Core Registers

Incorrect frequency of mgmt_ifc_clock

Make sure that the frequency of the mgmt_ifc_clock matches that specified in the TimeQuest timing constraints.

Incorrect address decoding before targetting Interlaken core

Make sure that your design is correctly decoding the Avalon-MM address before it is driven into the Interlaken core.

Incorrect use of the management interface, violation of Avalon-MM specification

Monitor the Avalon-MM interface of the Interlaken core and confirm that your application is driving the interface according to the Avalon-MM specification,

Address presented is out of range of the Interlaken Memory Map space

Confirm that the address is targetting a register within the Interlaken address space.

Timing violations

Check for timing violations or for incorrect timing constraints in TimeQuest.

Version history
Revision #:
1 of 1
Last update:
‎06-21-2019 07:24 PM
Updated by:
 
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