The LPDDR2 standard uses a double data rate command and address bus which replpaces the #CAS, #RAS. #WE, BA and A vectors which are used for previous DRAM standards. I made this simple decoder to decode the command and the rsulting address from the 10-bit LPDDR2 CA bus. The decoder only decodes LPDDR2-SX (SDRAM) commands and not LPDDR2-N (NVM).
The files for the decoder may be downloaded from here: File:Lpddr2 ca decoder.zip
The decoder is VHDL. The inputs are connected to the same inputs as the LPDDR2 memory component that you want to monitor in your testbench. The ports are listed below:
LPDDR2 CA decoder ports
Memory clock. This signal should be connected to the same signal as CK input on the LPDDR2 memory that is being monitored.
Memory CA. This signal should be connected to the same signal as CA0 - CA9 inputs on the LPDDR2 memory that is being monitored.
Enumerated type which shows the command which is valid for the current clock cycle. This is valid on the falling edge of mem_ck. The symbols match those used in section 3.2 of JESD209-2E
Bank address. This is updated on Activate, Write, Read and Precharge commands.
Row address. This is updated on Activate commands.
Column address. This is updated on Write and Read commands.
Auto Precharge. This is updated on Read and Write commands.
Mode Register address. This is updated on MRW and MRR commands.
Mode Register data. This is updated on MRW and MRR commands.
The decoder makes use of the lpddr2_ca_decoder_types.vhd package which is included in the zip archive.
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