Marvell 88E1111 PHY Configuration Steps

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Marvell 88E1111 PHY Configuration Steps

Arria 10 SoC Development Kit (RJ-45 / SGMI Auto-Negotiation / Triple-Speed Ethernet IP Core)

1. Keep Marvell PHYs' RESET_N pin (enta_resetn and enetb_resetn) to be low for 10 ms (Marvell PHY spec is 10 ms min.). If the reset duration is short, the Marvell PHY might transmit K30.7 (octet value 0xFE) instead of IDLE to the Arria 10 device.
2. Wait for 5 ms after the reset deassertion (Marvell PHY spec is 5 ms min.). MDIO is ready now.
3. Configure the Marvell PHY through TSE's MDIO
   1. Write 0x0000 to 0x10 (TSE MAC register: mdio_addr1 // Marvell PHY address is 0x00)
   2. Write 0x1140 to 0xA0 (TSE MDIO1 space: Marvell PHY addr 0x0 // Copper Full Duplex)
   3. Write 0x0F00 to 0xA9 (TSE MDIO1 space: Marvell PHY addr 0x9 // Advertise Full and Half Duplex support)
   4. Write 0x01E1 to 0xA4 (TSE MDIO1 space: Marvell PHY addr 0x4 // Advertise Full and Half Duplex support)
   5. Write 0x1340 to 0xA0 (TSE MDIO1 space: Marvell PHY addr 0x0 // Software Reset)
4. Configure the TSE PCS as SGMII Auto-Negotiation (for detailed steps, see "Triple-Speed Ethernet System with SGMII" in the TSE User Guide)
5. Configure the TSE MAC (for detailed steps, see "Triple-Speed Ethernet System with MII/GMII or RGMII" in the TSE User Guide)

Note: Marvell PHYs' RESET_N pins are connected to the Arria 10 SoC device through the MAX V device that is called io_max5. 

max5.vhd of io_max5

eneta_reset <= fpgaio_p(6) ;

enetb_reset <= fpgaio_p(7) ;

max5.qsf of io_max5

set_location_assignment PIN_J3 -to fpgaio_p[6]

set_location_assignment PIN_J4 -to fpgaio_p[7]

set_location_assignment PIN_E9 -to eneta_reset

set_location_assignment PIN_C9 -to enetb_reset

a10_fpga_sgmii.qsf of Arria 10 SoC

set_location_assignment PIN_N1 -to eneta_resetn // Schematic node name: fpgaio_p[6]

set_location_assignment PIN_R2 -to enetb_resetn // Schematic node name: fpgaio_p[7]