Arria 10 SoC Development Kit (RJ-45 / SGMI Auto-Negotiation / Triple-Speed Ethernet IP Core)
Keep Marvell PHYs' RESET_N pin (enta_resetn and enetb_resetn) to be low for 10 ms (Marvell PHY spec is 10 ms min.). If the reset duration is short, the Marvell PHY might transmit K30.7 (octet value 0xFE) instead of IDLE to the Arria 10 device.
Wait for 5 ms after the reset deassertion (Marvell PHY spec is 5 ms min.). MDIO is ready now.
Configure the Marvell PHY through TSE's MDIO
Write 0x0000 to 0x10 (TSE MAC register: mdio_addr1 // Marvell PHY address is 0x00)
Write 0x1140 to 0xA0 (TSE MDIO1 space: Marvell PHY addr 0x0 // Copper Full Duplex)
Write 0x0F00 to 0xA9 (TSE MDIO1 space: Marvell PHY addr 0x9 // Advertise Full and Half Duplex support)
Write 0x01E1 to 0xA4 (TSE MDIO1 space: Marvell PHY addr 0x4 // Advertise Full and Half Duplex support)
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