Modeling Copper Surface Roughness for Multi-gigabit Channel Designs

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Modeling Copper Surface Roughness for Multi-gigabit Channel Designs

Modeling Copper Surface Roughness for Multi-gigabit Channel Designs


Multi-gigabit transceiver channel designs involve selecting the appropriate dielectric material for the PCB, managing the channel routing to compensate for the material’s fiber-glass weave effects and optimizing various channel discontinuities to minimize loss. Material selection and fiber-glass weave considerations for gigabit channel designs are presented in application notes AN528 (PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing) and AN613 (PCB Stackup Design Considerations for Altera FPGAs), while discontinuity considerations for signal vias and channel capacitors surface mount pads are discussed in AN529 (Via Optimization Techniques for High Speed Channel Designs) and AN530 (Optimizing Impedance Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs), respectively. In addition to these considerations, channel loss can be exacerbated by the surface roughness of the copper trace conducter that makes up the channel. Because this effect is unaccounted for in traditional 3-D modeling and simulation tools, simulation results can lead to very optimistic channel performance prediction when compared to actual channel performance measurements. As a result, designers must account for copper surface roughness when modeling multi-gigabit transceiver channel designs. In this application note, a test trace design is modelled using Ansoft’s HFSS 3-D electromagnetic field simulation tool and the insertion loss result is correlated with actual Vector Network Analyzer (VNA) measurements to better understand the effects of copper surface roughness and validate the simulation methodology.

Copper Surface Roughness

Copper clad foils used in the construction of PCB copper layers are generally constructed by one of two techniques: (1) Electrodeposited (ED) copper and (2) Rolled copper.

ED copper is formed by rotating a negatively charged metal drum in a positively charged liquid copper sulfate solution tank. This process allows the positively charged copper in the solution to migrate towards the negatively charged drum. As the copper deposits onto the turning drum, it forms a thin but rough copper foil. The thickness and roughness of the copper is dependent on the voltage potential between the drum and tank, as well as the rotational speed of the drum.1The roughness of the copper is typically specified in microns and depicted as a root mean square (RMS) or average value.

Rolled copper is formed by cold pressing thicker sheets of copper between heavy steel rollers into thinner copper foils. This process of flattening the copper sheets creates a copper foil with a very smooth surface. This smoothness mitigates surface roughness losses but can create manufacturabiltiy and reliability concerns, as having a roughened surface enhances the material’s peel strength and lessens the likelihood of layer delamination during multiple high-temperature manufacturing or rework cycles.

As a result, ED copper is generally preferred and more commonly used over rolled copper for reliable PCB manufacturing and production. However, when using ED copper, the additional copper surface roughness losses must be included for accurate simulation modeling.

Surface Rouhgness Correction

As frequency increases, the majority of current flow is pushed to the outer surface of the copper conductor due to the skin effect. The penetration depth of this surface current flow (skin depth) is a function of frequency. As frequency increases, the skin depth is reduced. At frequencies where the skin depth approaches the average roughness of the copper, this current flow is further impeded by the surface roughness of the copper, causing increased resistance and higher signal attenuation and loss.

One method to compensate for this added attenuation and achieve better simulation accuracy is to add a surface roughness correction factor to the simulated signal attenuation as shown in equations (1) and (2)

Equation1.jpg (Click here for image)

Simulation Modeling Versus Measurement Correlation

To understand the effects of copper surface roughness, consider the following structure shown in Figure 1. For this structure, HFSS simulated insertion loss and attenuation results with and without the effects of copper surface roughness are compared with VNA measurement data for the same structures realized in an actual PCB design.

Test Structure

This structure models a six-inch 100Ω loosely-coupled microstrip differential pair copper trace referencing a solid copper ground plane with a Rogers 4350B dielectric core in between as shown in Figure 1. For Rogers 4350B, a relativity permittivity (εr) of 3.66 and loss tangent (tan(δ)) of 0.004 is used in the simulation. An average copper surface roughness of 1μ is used.

Figure 1 – HFSS modelled 6in-microstrip diff-pair on Rogers 4350B dielectric- Surface_Roughness_Fig1.jpg  (Click here for image)

Since the HFSS insertion loss (S21) result does not include the effects of the copper roughness, the simulated S21 data must be modified to add the surface roughness correction factor as described by equation (1).

The conversion from insertion loss magnitude |S21| in decibels (dB) to total attenuation in nepers follows equation (4)

Equation4.jpg (Click here for image)

Furthermore, since the total signal attenuation is a combination of dielectric and conductor attenuation, the correction factor must only be applied to the conductor attenuation (αcond) portion of the total attenuation. To separate αcond from αtot, use equation (5) and (6)

Equation5-6.jpg (Click here for image)

Once the conductor attenuation is determined and equation (1), (2), and (3) is applied to

include the copper surface roughness correction factor, the total attenuation and insertion

loss including the effects of surface roughness is obtained.

Figure 2 – Simulated αtot (with & without roughness correction) vs measurement- Surface_Roughness_Fig2.jpg (Click here for image)

Figure 3 – Simulated S21 (with & without roughness correction) vs measurement- Surface_Roughness_Fig3.jpg  (Click here for image)

Figures 2 and 3 show the resulting simulated attenuation and insertion loss plots (with and without copper surface roughness correction) versus the VNA measurements for the actual PCB trace. The correlation between measurement and simulation with surface roughness correction is well achieved wheras the simulated result without surface correction significantly underestimates the actual trace losses.


Because existing modeling and simulation tools do not include the roughness of the copper conductor, simulation results can severely underpredict the actual loss of the copper trace even when the structure is precisely modeled by advanced 3-D modeling tools. To account for this added loss in simulations and accuractely predict conductor losses, a surface roughness correction factor must be added to the simulated attenuation. This application note presents the methodology to accurately model copper conductor attenuation by including a correction factor for the surface roughness of the copper. Simulation results versus actual board measurement data is used to validate the simulation methodology and achieve better loss prediction.


1. Base Materials for High Speed, High Frequency PC Boards, Rick Hartley, PCB&A, Mar 2002

2. Signal Integrity – Simplified, Dr. Eric Bogatin, Prentice Hall Professional Technical Reference, Upper Saddle River, NJ 07458, Dec 2006

3. A Practical Method for Modeling PCB Transmission Lines with Conductor Surface Roughness and Wideband Dielectric Properties, Tao Liang, Stephen Hall, Howard Heck & Gary Brist

4. Non-Classical Conductor Losses Due to copper Foil Roughness and Treatment, Gary Brist, Stephen Hall, Sidney Clouser, & Tao Liang

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Last update:
‎06-25-2019 07:18 PM
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