The ability to configure your FPGA with a new image from files stored on a remote PC via ethernet
The NEEK when powered up and connected to a network port actually serves up a web page. Through this web page you can browse to, download and configure the FPGA on the NEEK with a new image.How does the NEEK demonstrate Remote System Update?
How does Remote System Update work on the NEEK?
When your NEEK board is connected to the network it serves up a web page. (The contents of this web page are stored in the SD Card in a folder called webserver_html
From any PC you can view this web page by simply typing the correct IP address on a web browser.
By following the instructions displayed on the HTTP forms on the web page you can browse to and load a new FPGA image stored on the PC
Using the Program Flash button you can remote program (via the ethernet link) the on board flash
Using the Reset button on the web page you can reconfigure the FPGA with the newly downloaded Flash image.
What do I need to get started?
The Nios II Embedded Evaluation Kit
The latest application selector with Remote system update facility programmed on the board.
A PC with a connection to a working Ethernet Port
A separate working ethernet port to connect your NEEK board to
A FPGA image (.FLASH) files to update the board with. These must be present on your PC.
How do I try out the Remote System Update feature on my NEEK?
STEP 1: Apply power to the NEEK board by plugging the power cable and pressing switch SW1.
The application selector will appear, and you will see a button on the botton right that says "Not Connected"
STEP 2:Using an Ethernet Cable, connect the Ethernet RJ-45 jack on the LCD Multimedia HSMC to a working network port.
The connection to the ethernet port wil by detected and attempts to find a suitable IP address will be take place during which time you should see "Connecting..." message.
Getting an IP address may take a few minutes
STEP 3: On completion the acquired IP address will be displayed on the LCD Screen.
STEP 4: Ensure your host PC is connected to a working network port. Launch a web browser window.
STEP 5: On the host PC, in the web browsertype in the IP address displayed on the LCD screen e.g. (type 22.214.171.124)
You should now see a web page displayed on the web browser. The contents of this page are stored in the webserver_htmlfolder on your SD Card
STEP 6: On the upper left hand side on the web form, click on the link under "Read the Instructions".
STEP 7: For this next step you will need to a new FPGA image to download to the Flash on your host PC.
An FPGA image is a FPGA hardware image (.SOF) and an FPGA software image (.ELF) that has been converted to a .FLASH file.
If you have your own FPGA image, i.e. a then refer to section "How do I create my own .FLASH files for Remote System update?"
If you do not have your own FPGA image simply you can download one from the <a href="/RemoteSystemUpdateExamples">Remote System Update examples page and add to your host PC
STEP 8': On the remote system update instructions page, you will see a CFI 'Flash Upload section. Click Browse and navigate to the location of the Flash file containing the FPGA hardware image to be downloaded. Click Open.
STEP 9: On the web page click Upload.
Wait while the Flash file is transferred to your board. On completion you will be directed to Program CFI Flash button.
STEP 10: Click on Program Flash. Depending on the size of the file this step should take a few minutes to complete.
STEP 11: Click on Return to instructions, and repeat the previous 2 steps but this time browse to and Upload the Flash file containing the FPGA software image. (If your application has no software portion then ignore this step and go to the next step). Upon completion you will be directed to the Reset System option.
STEP 12: Click on Reset System button. The FPGA should now reconfigure form the newly programmed contents of the Flash.
How can I create my own .FLASH files for Remote system Update?
To create .Flash files you must have install the Nios II EDS and Quartus II FPGA design software.
If your FPGA hardware image has a CPU then make sure that the CPU reset address is configured to external flash at offset 0x0
Compile your FPGA hardware in Quartus II which will result in a SRAM object file (.SOF) i.e. the FPGA hardware image.
Compile the FPGA software in the standard fashion, the result of the compile is the Executable Linked Format file (.ELF) i.e. the FPGA software image
METHOD 1: USE 2 COMMANDS
On your host PC, launch a Nios II Command Shell form Start -> Programs -> Altera -> Nios II <versoin> EDS -> Nios II Command Shell
From within the Nios II Command Shell navigate to where your SOF file is located and create your hardware Flash image by typing
Method 2: <a href="/RemoteSystemUpdateExamples">USE A SCRIPT
How can I implement Remote System Update feature for my design?
Use the Application Selector with Remote System Update example design as a starting point for your default FPGA image. Use your design as the "Production" image that may be updated as your design evolves.
You can get the Application Selector design examples from your Nios II Embedded Evaluation Kit Install CD or my visiting the www.altera.com/nios2eval page.