Preserving Intel® Stratix® 10 and Intel Agilex® FPGA E-tile transceivers when channels are unused

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Preserving Intel® Stratix® 10 and Intel Agilex® FPGA E-tile transceivers when only some of the channels are unused

Description

This forum article is dedicated to users that want to preserve some unused channels in their Intel® Stratix® 10 or Intel Agilex® FPGA E-tile transceiver.  The E-tile transceiver PHY user guide shows examples of how to preserve unused channels but is missing some key information when preserving channels within an E-tile or over multiple E-tiles where it is supporting some used and some unused channels.  

Documentation Links

The following user guide can be used as a reference for this article:

E-Tile Transceiver PHY User Guide 

Section 3.1.10. Unused Transceiver Channels 

Preserving ALL E-tile channels

The following qsf can only be used to preserve ALL E-tile channels within the Stratix 10 or Agilex FPGA.  So, if you have a Stratix 10 with 3 E-tiles, this constraint can only be used to preserve all channels on all 3 E-tiles.

set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON

The user guide goes on to show how to properly assign input clocks and HSSI parameters

#instance assignments for 3 tiles
set_location_assignment <REFCLK_PIN_1> -to <REFCLK_PORT_1>
set_instance_assignment -name HSSI_PARAMETER "refclk_divider_use_as_bti_clock=true" -to <REFCLK_PORT_1>
set_instance_assignment -name HSSI_PARAMETER “refclk_divider_input_freq=<frequency in Hz>" -to <REFCLK_PORT_1>

set_location_assignment <REFCLK_PIN_2> -to <REFCLK_PORT_2>
set_instance_assignment -name HSSI_PARAMETER "refclk_divider_use_as_bti_clock=true" -to <REFCLK_PORT_2>
set_instance_assignment -name HSSI_PARAMETER "refclk_divider_input_freq=<frequency in Hz>" -to <REFCLK_PORT_2>

set_location_assignment <REFCLK_PIN_3> -to <REFCLK_PORT_3>
set_instance_assignment -name HSSI_PARAMETER "refclk_divider_use_as_bti_clock=true" -to <REFCLK_PORT_3>
set_instance_assignment -name HSSI_PARAMETER "refclk_divider_input_freq=<frequency in Hz>" -to <REFCLK_PORT_3>

Preserving some E-tile channels

If you plan on using even just one E-tile channel with plans to use the remainder at a future date, you will be required to preserve all other channels on all E-tiles within either your Stratix 10 or Agilex FPGA. 

On the Stratix 10 TX SI development kit Bank 8C E-tile, here is an example that has 8 used channels and 16 unused channels.  Ordering in the qsf is very important.  The preserve assignments must come first, followed by the reference clock input assignment and IO standard assignment, followed by the used channel pin assignments, and finally followed by the HSSI_PARAMETER assignments.

set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to R51 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to P54 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to N51 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to M54 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to L51 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to K54 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to J51 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to H54 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to G51 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to F54 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to D54 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to E51 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to C45 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to A45 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to D42 -entity s10_tx_dev_stk_top
set_instance_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON -to B42 -entity s10_tx_dev_stk_top

set_location_assignment PIN_AB37 -to i_CLK_8C_PLL_176M
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to i_CLK_8C_PLL_176M -entity s10_tx_dev_stk_top

set_location_assignment PIN_E39 -to MXPA_RX_P[0]
set_location_assignment PIN_G39 -to MXPA_RX_P[1]
set_location_assignment PIN_H42 -to MXPA_RX_P[2]
set_location_assignment PIN_J39 -to MXPA_RX_P[3]

set_location_assignment PIN_E38 -to MXPA_RX_N[0]
set_location_assignment PIN_G38 -to MXPA_RX_N[1]
set_location_assignment PIN_H41 -to MXPA_RX_N[2]
set_location_assignment PIN_J38 -to MXPA_RX_N[3]

set_location_assignment PIN_H36 -to MXPB_RX_P[0]
set_location_assignment PIN_K36 -to MXPB_RX_P[1]
set_location_assignment PIN_C33 -to MXPB_RX_P[2]
set_location_assignment PIN_E33 -to MXPB_RX_P[3]

set_location_assignment PIN_H35 -to MXPB_RX_N[0]
set_location_assignment PIN_K35 -to MXPB_RX_N[1]
set_location_assignment PIN_C32 -to MXPB_RX_N[2]
set_location_assignment PIN_E32 -to MXPB_RX_N[3]

set_location_assignment PIN_C51 -to MXPA_TX_P[0]
set_location_assignment PIN_A51 -to MXPA_TX_P[1]
set_location_assignment PIN_D48 -to MXPA_TX_P[2]
set_location_assignment PIN_B48 -to MXPA_TX_P[3]

set_location_assignment PIN_C50 -to MXPA_TX_N[0]
set_location_assignment PIN_A50 -to MXPA_TX_N[1]
set_location_assignment PIN_D47 -to MXPA_TX_N[2]
set_location_assignment PIN_B47 -to MXPA_TX_N[3]

set_location_assignment PIN_C39 -to MXPB_TX_P[0]
set_location_assignment PIN_A39 -to MXPB_TX_P[1]
set_location_assignment PIN_B36 -to MXPB_TX_P[2]
set_location_assignment PIN_A33 -to MXPB_TX_P[3]

set_location_assignment PIN_C38 -to MXPB_TX_N[0]
set_location_assignment PIN_A38 -to MXPB_TX_N[1]
set_location_assignment PIN_B35 -to MXPB_TX_N[2]
set_location_assignment PIN_A32 -to MXPB_TX_N[3]

set_instance_assignment -name HSSI_PARAMETER "refclk_divider_enable_termination=enable_term" -to i_CLK_8C_PLL_176M -entity s10_tx_dev_stk_top
set_instance_assignment -name HSSI_PARAMETER "refclk_divider_enable_3p3v=enable_3p3v_tol" -to i_CLK_8C_PLL_176M -entity s10_tx_dev_stk_top
set_instance_assignment -name HSSI_PARAMETER "refclk_divider_enable_hysteresis=disable_hyst" -to i_CLK_8C_PLL_176M -entity s10_tx_dev_stk_top
set_instance_assignment -name HSSI_PARAMETER "refclk_divider_input_freq=156250000" -to i_CLK_8C_PLL_176M -entity s10_tx_dev_stk_top
set_instance_assignment -name HSSI_PARAMETER "refclk_divider_powerdown_mode=false" -to i_CLK_8C_PLL_176M -entity s10_tx_dev_stk_top
set_instance_assignment -name HSSI_PARAMETER "refclk_divider_use_as_BTI_clock=true" -to i_CLK_8C_PLL_176M -entity s10_tx_dev_stk_top

Notice in the above that the HSSI_PARAMETER refclk_divider_use_as_BTI_clock=true is setup across the entire E-tile and will cover the unused channels.  A false setting will only apply if the unused channels do not need to be preserved or if all channels on the E-tile are being used.

Notice in the above assignments that the bold underlined R51 is the pin number only.  It does not use “PIN_R51” like when making a pin assignment, just the raw name of the pin “R51”.