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RapidIO Gen1 Debug Checklist

RapidIO Gen1 Debug Checklist



reset_nMonitor these signals

port_initialized

rx_freqlocked

rx_errdetect

packet_transmitted

packet_cancelled

packet_accepted

packet_not_accepted

packet_retry

rx_packet_dropped

packet_crc_error

symbol_error

port_error

char_error

Unable to establish a link

Confirmed by observing that port_initialized never goes HI or by reading always 1'b1 from register 0x158 bit 0

Link partner does not match core configuration.

Confirm that link partner is programmed to run at expected data rate and mode (lane width).

Core is in reset. Use SignalTAP to monitor "reset_n".

Fix reset logic so that the core is not held in reset.

Unable to acquire frequency lock. Use SignalTAP to monitor "rx_freqlocked".

Incorrect frequency for reference clock.

Confirm correct reference clock frequency.

Incorrect IO Standard for reference clock input.

Select the correct IO Standard to match the source for the reference clock.

Incorrect IO Termination.

Confirm correct On-Chip Termination or correct On-Board Termination.

Incorrect Pin Assignment for reference clock input.

Make sure that you are assigning the correct pin to the reference clock. Review board layout and confirm.

Incorrect Pin Assignment for serial line/s.

Make sure that you are assigning the correct pins to the rx and tx serial lines. Review board layout and confirm

Incorrect transceiver analog settings.

Perform an internal serial loopback test. This is done by setting the transceivers in serial loopback mode. If the link comes up in this mode, then your issue may have to do with the analog settings. In this case use the transceiver toolkit to determine the best analog settings. Then apply these settings to the RapidIO transceivers. This can be done by using the Reconfiguration Controller or by applying the settings in your .qsf file. If the serial loopback test fails, then contact the factory.

Timing requirements not met.

Run Time Quest and fix any setup or hold time violations.

Incorrectly defined clocks

Confirm requirements applied in .sdc file. The RapidIO core comes with an .sdc file. The .sdc file is generated with assumption that the RapidIO core clock port names are the final clock names in a complete design. This is not normally the case, and the user has to apply the correct clock names to the .sdc file.

Unconstrained clocks

Use TimeQuest to report any unconstrained clocks. Fix any unconstrained clocks.

Timing models not final for your device

If available, upgrade to a Quartus II ACDS release that has final timing models for your device.

Incorrect transceiver analog settings.

Perform an internal serial loopback test. This is done by setting the transceivers in serial loopback mode. If the link comes up in this mode, then your issue may have to do with the analog settings. In this case use the transceiver toolkit to determine the best analog settings. Then apply these settings to the RapidIO transceivers. This can be done by using the Reconfiguration Controller or by applying the settings in your .qsf file. If the serial loopback test fails, then contact the factory.

In 2x or 4x modes, missaligned lanes.

Excessive lane-to-lane skew

Ensure matching board traces for lanes.

No Transceiver Reconfiguration Controller

Instantiate a reconfiguration controller and connect it correctly.

Transceiver Reconfiguration Controller is not connected correctly.

Unreliable link

Unable to maintain frequency lock or excessive bit error rate. Monitor “rx_freqlocked” and "rx_errdetect".

Incorrect transceiver analog settings

Perform an internal serial loopback test. This is done by setting the transceivers in serial loopback mode. If the link comes up in this mode, then your issue may have to do with the analog settings. In this case use the transceiver toolkit to determine the best analog settings. Then apply these settings to the RapidIO transceivers. This can be done by using the Reconfiguration Controller or by applying the settings in your .qsf file. If the serial loopback test fails, then contact the factory.

Unable to transmit write transactions

Packet does not make it out of the core, this is confirmed by no pulse on "packet_transmitted".

Output disabled

Enable "OUT_PENA" in register 0x15C, Port 0 Control CSR.

Disabled IO Slave Mapping Window

Enable "WEN" in register/s Input/Output Slave Mapping Window n Mask, 0x10404, 0x10414, etc.

Avalon-MM address out of range

Make sure that the value on "io_s_wr_address" bus is within the Base and Mask specifed in Input/Output Slave Address Mapping Windows in register 0x10400 - 0x104F0 and 0x10404 - 0x104F4.

Violation of Avalon-MM Interface specification

Confirm that the transactions presented on the "io_s_wr" interface conform to the Avalon-MM specification. If the burst writes are being presented violate the specification, the burst writes will not be honored.

Target processing endpoint does not receive write transactions.

Packet makes it out of the core, but the link partner or target processing endpoint does not account for it.

Incorrect Destination ID

Make sure that the Destination ID programmed in register 0x1040c – 0x104fc, Input/Output Slave Mapping n Control, matches the Base Device ID of the targeted processing endpoint.

DeviceID width mismatch

Make sure that the width of the DeviceID matches the width expected by any switches and the target processing endpoint. The width of the DeviceID is selected when generating the RapidIO MegaCore using the MegaWizard GUI.

AckIDs are not synchronized. This is determined by examining the RapidIO Local AckID CSR 0x148 and the link partner's Local AckID CSR. The corresponding INBOUND_ACKID and OUTBOUND_ACKID values should match. To synchronize the AckIDs:

Reset both link partners to reset the AckIDs to zero.

Configure the link partner's AckIDs to match by writing matching values into their Local AckID CSRs.

Clear link partner's AckIDs and perform a reset of the RapidIO core.

Unable to transmit NREAD transactions

Packet does not make it out of the core, this is confirmed by no pulse on "packet_transmitted"

Output disabled

Enable "OUT_PENA" in register 0x15C, Port 0 Control CSR.

Disabled IO Slave Mapping Window

Enable "WEN" in register/s Input/Output Slave Mapping Window n Mask, 0x10404, 0x10414, etc.

Avalon-MM address out of range

Make sure that the value on "io_s_rd_address" bus is within the Base and Mask specified in the Input/Output Slave Address Mapping Windows in registers 0x10400 - 0x104F0 and 0x10404 - 0x104F4.

Violation of Avalon-MM Interface specification

Confirm that the transactions presented on the "io_s_rd_" interface conform to the Avalon-MM specification. If the burst writes are being presented violate the specification, the burst writes will not be honored.

Target processing endpoint does not receive NREAD transactions.

Packet makes it out of the core, but the link partner or target processing endpoint does not account for it.

Incorrect Destination ID

Make sure that the Destination ID programmed in register 0x1040c – 0x104fc, Input/Output Slave Mapping n Control, matches the Base Device ID of the targeted processing endpoint.

DeviceID width mismatch

Make sure that the width of the DeviceID matches the width expected by any switches and the targeted processing endpoint. The width of the DeviceID is selected when generating the RapidIO MegaCore using the MegaWizard GUI.

AckIDs are not synchronized. This is determined by examining the RapidIO Local AckID CSR 0x148 and the link partner’s Local AckID CSR. The corresponding INBOUND_ACKID and OUTBOUND_ACKID values should match. To synchronize the AckIDs:

Reset both link partners to reset the AckIDs to zero.

Configure the link partners’ AckIDs to match by writing matching values into their Local AckID CSRs.

Clear link partner’s AckIDs and perform a reset of the RapidIO core.

Unable to transmit Maintenance Transactions.

Packet does not make it out of the core, this is confirmed by no pulse on "packet_transmitted".

Output disabled

Enable “OUT_PENA” in register 0x15C, Port 0 Control CSR.

Disabled TX Maintenance Mapping Window

Enable “WEN” in register, Tx Maintenance Mapping Window n Mask 0x10104 - 0x101F4.

Avalon-MM address out of range

Make sure that the value on “mnt_s_address” bus is within the Base and Mask specified in Tx Maintenance Mapping Windows in registers 0x10100 – 0x101f0 and 0x10104 – 0x101f4.

Violation of Avalon-MM Interface specification

Confirm that the transactions presented on the “mnt_s_” interface conform to the Avalon-MM specification. If the read or write bursts are being presented violate the specification, then the burst writes will not be honored.

Target processing endpoint does not receive Maintenance Transactions

Packet makes it out of the core, but the link partner or target processing endpoint does not account for it.

Incorrect Destination ID

Make sure that the Destination ID programmed in register 0x1010c – 0x101fc, Tx Maintenance Mapping Window n Control, matches the Base Device ID of the targeted processing endpoint.

DeviceID width mismatch

Make sure that the width of the DeviceID matches the width expected by any switches and the targeted processing endpoint. The width of the DeviceID is selected when generating the RapidIO MegaCore using the MegaWizard GUI.

AckIDs are not synchronized

Reset both link partners to reset the AckIDs to zero.

Configure the link partners’ AckIDs to match by writing matching values into their Local AckID CSRs.

Clear link partner’s AckIDs and perform a reset of the RapidIO core.

Unable to transmit Doorbell Transactions.

Packet does not make it out of the core, this is confirmed by no pulse on "packet_transmitted".

Output disabled

Enable “OUT_PENA” in register 0x15C, Port 0 Control CSR.

Doorbell TX Buffer full. Determined by reading the Tx Doorbell Status 0x10. A maximum of 16 outstanding doorbell messages are supported. No new Doorbell messages will be accepted at the drbell_s_wr interface unless the number of outstanding doorbell messages is less than 16.

Wait until there is room in the Doorbell TX Buffer to transmit a doorbell

If no doorbell response is received within the Response Timeout value, than the oldest doorbell message will timeout. The user must retrieve the completed tx doorbell message and its status.

Violation of Avalon-MM Interface specification

Confirm that the transactions presented on the “drbell_s_” interface conform to the Avalon-MM specification. If the read or write bursts are being presented violate the specification, then the burst writes will not be honored.

Target processing endpoint does not receive Doorbell Message.

Packet makes it out of the core, but the link partner or target processing endpoint does not account for it.

Incorrect Desitnation ID

Make sure that the Destination ID programmed in register 0x0c, Tx Doorbell, matches the Base Device ID of the targeted processing endpoint.

DeviceID width mismatch

Make sure that the width of the DeviceID matches the width expected by any switches and the targeted processing endpoint. The width of the DeviceID is selected when generating the RapidIO MegaCore using the MegaWizard GUI.

AckIDs are not synchronized

Reset both link partners to reset the AckIDs to zero.

Configure the link partners’ AckIDs to match by writing matching values into their Local AckID CSRs.

Clear link partner’s AckIDs and perform a reset of the RapidIO core.

RapidIO core does not respond to Maintenance Transactions issued by link partner.

Input disabled

Enable “IN_PENA” in register 0x15C, Port 0 Control CSR.

Incorrect Base Device ID

Make sure that the Maintenance Transactions have a Destination ID value that matches the RapidIO core Base Device ID.

DeviceID width mismatch

Make sure that the Maintenance Transactions have a matching width to the Base Device ID in 0x60.

Maintenance Master not connected to System Maintenance Slave

Confirm that the RapidIO “mnt_m” port is connected to the “sys_mnt_s” port. If design was generated with QSYS, check the patch panel in QSYS. If the design was not done in QSYS, then check your connectivity in your design.

Maintenance Master not connected correctly to System Maintenance Slave

Check for correct connectivity between the “mnt_m” output port to the “sys_mnt_s” input port.

RapidIO core does not respond to Write transactions.

Input disabled

Enable “IN_PENA” in register 0x15C, Port 0 Control CSR.

Incorrect Base Device ID

Make sure that the Write Transactions have a Destination ID value that matches the RapidIO core Base Device ID.

Device ID width mismatch

Make sure that the Write Transactions have a matching width to the Base Device ID in 0x60.

IO Master Window disabled

Enable “WEN” in register Input/Output Master Mapping Window n Mask, 0x10304 - 0x103f4.

RapidIO core does not respond to NREAD requests.

Input disabled

Enable “IN_PENA” in register 0x15C, Port 0 Control CSR.

Incorrect Base Device ID

Make sure that the NREAD Transactions have a Destination ID value that matches the RapidIO core Base Device ID.

Device ID width mismatch

Make sure that the NREAD Transactions have a matching width to the Base Device ID in 0x60.

IO Master Window disabled

Enable “WEN” in register Input/Output Master Mapping Window n Mask, 0x10304 - 0x103f4.

"io_m_rd_readdatavalid" is not responding to "io_m_rd_read" request

Make sure that the Avalon-MM slave connected to the “io_m_rd” port is functionality correct. Check for the address targeting a legal address space.

RapidIO core does not respond to Doorbell Messages.

Target processing endpoint did not receive a Response.

Input disabled

Enable “IN_PENA” in register 0x15C, Port 0 Control CSR.

Incorrect Base Device ID

Make sure that the Doorbell Messages have a Destination ID value that matches the RapidIO core Base Device ID.

Device ID width mismatch

Make sure that the Doorbell Messages have a matching width to the Base Device ID in 0x60.

No Doorbell module included when the core was generated

Regenerate the RapidIO core and include a Doorbell Module.

RX Buffer in Doorbell module is full

Read any received Doorbell Messages from the Doorbell RX Buffer, to make room for new incoming Doorbell Messages.

Link partner's Response TimeOut value is too low

Make sure that the processing endpoint sending the Doorbell Messages is timing the Doorbell Response too soon. Allow time for the Doorbell Message to make its round trip. If the doorbell message is timing out at the source, then adjust the Response Timeout value of the originating processing endpoint.

After sending several NREADs, the core cannot send anymore NREADs.

Unavailable Transaction IDs, only 13 outstanding NREAD requests are supported. A Response to an NREAD has not been received to free up a Transaction ID.

Allow more time for the Response to an NREAD request to arrive.

An NREAD Response will be timeout if not received within the time specified in the Response Timeout value in register 0x124.

No read data is received for a generated NREAD request.

It is taking longer than predicted to get the Response

Allow more time for the Response, the read data to arrive.

Incorrect Destination ID used in NREAD request.

Check the Destination ID field in the Input/Output Slave Mapping Window n Control. It must match the Base Device ID of the target processing endpoint.

After sending an NREAD, io_s_rd_readerror is asserted.

The read response timed out

increase the TimeOut value in register 0x124

A response was received which indicated an error.

Check link partner's availability of resources

After sending several NWRITE_Rs, the core cannot issue anymore NWRITE_Rs.

Unavailable Transaction IDs, only 13 outstanding NWRITE_R transactions are supported. A Response to an NWRITE_R has not been received to free up a Transaction ID.

Wait until there are free Transaction IDs. When available, the io_s_wr_waitrequest signal will be removed (go LOW).

After sending 16 Doorbell Messages, the core cannot issue any more.

Only 16 outstanding Doorbell Messages are supported. A response to a doorbell message has to be received before another message can be transmitted.

Check link partner to confirm that it is receiving the Doorbell Message and that it is generating a response.

The link locks up after some time of successful exchange of traffic.

AckIDs lose synchronization. This is determined by examining the RapidIO Local AckID CSR 0x148 and the link partner’s Local AckID CSR. The corresponding INBOUND_ACKID and OUTBOUND_ACKID values should match.

High Bit Error rate. Monitor the “rx_errdetect” signal to determine if excessive bit errors are present. See section above, “Unreliable link”, for resolution.

RapidIO core resets its AckIDs while the link partner does not.

• Reset both link partners to reset the AckIDs to zero.

• Configure the link partners’ AckIDs to match by writing matching values into their Local AckID CSRs.

Clear link partner’s AckIDs and perform a reset of the RapidIO core.

Output Port is in the Output Error Stopped state

Force the link partner to send a Link-Request Input Status Control Symbol. This feature is available in most link partners.

Input port is in the Input Error Stopped state

Transmit a Link-Request Input-Status Control Symbol. This feature is available in the RapidIO II MegaCore.

If using RapidIO Gen 1, then toggle the "PORT_DIS" bit in register 0x15C.

Poor performance

Shallow rx buffers in link partner. This can cause Packet-Retrys, which will impact performance.

Monitor the Packet-Retrys at the link partner. If excessive, try increasing the depth of the receive buffers. Congestion can sometimes be due to an oversubscribed output port in a switch. This would have to be addressed at the system level.

Poor link integrity which causes a high bit error rate. Link partners may spend time recovering the link, which impacts performance. Time recovering the link is time not spent exchanging real traffic.

Monitor the Packets Not Accepted count at both the link partner and the local RapidIO core. Check the link integrity and address why the link may be having excessive bit errors.

Port Link TimeOut or Port Response TimeOut value set too low.

A Link Timeout or Response Timeout value which is too low, can affect performance. Make sure that you are allowing enough time for Responses to make their way back to the source. Tune the Port Response TimeOut or Port Link TimeOut value in registers 0x124 and 0x120.

Unable to access local CSRs and CARs.

sys_mnt_s interface violation

Confirm that the transactions presented on the “sys_mnt_s_” interface conform to the Avalon-MM specification. If the read or write requests violate the specification, the requests will not be honored.

sys_mnt_s address not connected correctly

Make sure that the Avalon-MM master driving the sys_mnt_s port has the following address connectivity.

some_master_address[n:2]-> sys_mnt_s_address[16:0]

Version history
Revision #:
1 of 1
Last update:
‎06-27-2019 01:08 AM
Updated by:
 
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