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SDI II MegaCore Debug Checklist

SDI II MegaCore Debug Checklist

Introduction

This document describes the hardware debug flow and provides a checklist when testing out the Altera SDI II MegaCore. These guidelines help you verify your design, identify the problems, and resolve them quickly.

Most Frequent Ask Questions in SDI II

  • SDI II Tx Issue
  • Why SDI II output is not available?
  • Why the SDI II output have high jitter?
  • SDI II Rx Issue
  • Why SDI II Rx frame locked cannot be locked to the incoming SDI signal?
  • The rx_std shows incorrectly.
  • Why the frame locked always toggling?
  • Reconfiguration issue
  • The SDI II Rx cannot be locked when the incoming signal is switch to HD signal.
  • I have long locking time when received HD signal.

SDI II Debug Guideline Tips

  • Identify problem statement.

- Understand the problem statement/requirement.

- ACDS Version/IP Version/Target Device.

- SDI II IP Variant.

  • Triple rate/ Dual rate/ Single rate
  • Transceiver only, SDI II protocol only or both
  • Get the SDI II Verilog/VHDL Wrapper that generated by the Megawizard/IP Catalog GUI.

- Check if any known issue in solution or patch available.

- Timing Closure.

- Debug Information.

  • Hardware or Simulation
  • Tx issue or Rx issue
  • SD, HD or 3G signal
  • Simplify test case/environment if necessary
  • Duplicate the issue in Altera development kit.
  • Follow the debug flow for SDI II Tx Issue/Rx Issue on sections below in dev kit/customer board.

Debug Flow – SDI II Tx Issue


The following diagram shows an overview of the SDI II Tx debug flow. 




Debug Steps – SDI II Tx Implementation

  • Ensure all signals connected to SDI II MegaCore appropriately (refer to UG/reference design/example design).
  • Ensure all clocks are operating at their specified frequencies.

- reference clock, xcvr_refclk

- transmitter clock, tx_coreclk

- parallel clock, tx_pclk

  • Verify the board design – Signal integrity, driver and equalizer.

- Example: Ensure the driver used is support SD/HD/3G when user using SDI II triple rate mode.

  • Confirm data feed into signal tx_datain, tx_datain_valid tx_trs, tx_std, tx_ln, tx_vpid_byte*, tx_line_f*, tx_clkout, tx_pclk are correct. (signal tap)
  • Ensure cascade PLL is not applied to the transceiver reference clock (Not recommended).

Clock Frequency For SDI II Tx



  • The xcvr_refclk signal must be externally multiplexed in order to support 1/1.000 and 1/1.001 data rate factor. Extra xcvr_refclk_alt available for 1/1.001 data rate factor if “Tx PLL Dynamic Switching” option is enabled (Available for Arria V, Cyclone V, Stratix V and Arria V GZ devices).

Signal Tap – SDI II Tx Implementation

  • Ensure all the resets are released.
  • Ensure clock and transmited data, tx_datain are available.
  • Ensure tx_std and tx_trs are set correctly following the SDI standard defined by user.

Debug Steps – SDI II Tx Transceiver

  • Confirm all the transceiver signals are behave correctly. Verify tx_datain, tx_clkout, tx_pll_locked, tx_analogreset, tx_digitalreset, pll_powerdown. (you can found the signal by typing *phy|<signal name> into signal tap)

- Ensure all resets are released

- Ensure pll_locked is asserted

- Ensure data is available in signal tx_datain

Signal Tap - SDI II Tx Transceiver

  • tx_clkout might be same frequency and same phase with reference clock. If the signal tap clock triggered by reference clock, it will shows constant low or constant high.

- You may use tx_clkout as triggered clock to confirm the availability of the clock.

Debug Flow – SDI II Rx Issue


The following diagram shows an overview of the SDI II Rx debug flow. 




Debug Steps – SDI II Rx Implementation

  • Ensure all signals connected to SDI II MegaCore appropriately.

- Example: rx_coreclk_is_ntsc_paln must set to “LOW” when receiver controller clock is 148.5MHz or “HIGH” when reference clock is 148.35MHz.

  • Ensure all clocks are operating at their specified frequencies

- reference clock, xcvr_refclk

- receiver controller clock, rx_coreclk

  • Ensure reset is synchronous with reference clock.
  • Verify the board design – Signal integrity, driver and equalizer.

- Example: Ensure the equalizer used is support SD/HD/3G when user using SDI triple rate mode.

  • Enable “Increase Tolerance Level” option.
  • Signal tap rx_std, rx_dataout, rx_ln, rx_ln_b, rx_trs, rx_frame_locked, rx_trs_locked, rx_align_locked, rx_clkout to verify the problem.
  • Ensure cascade pll is not applied to the serial reference clock. (Not recommended).
  • Ensure the incoming SDI data is clean (within SDI jitter spec) and correct.

Clock Frequency For SDI II Rx



  • You can use either reference clock to received 1/1.000 and 1/1.001 data rate factor.

Signal Tap – SDI II Rx Implementation

  • Ensure all the resets are released.
  • Ensure rx_std, rx_dataout, rx_ln, rx_ln_b, rx_trs shows correctly.
  • Ensure rx_align_locked, rx_trs_locked, rx_frame_locked asserted.

Debug Steps – Reconfiguration

  • Important Notes:

- When power up, the transceiver is running at 3G/SD mode. Reconfiguration is not performed.

- Reconfiguration perform when incoming signal is switch from SD/3G to HD, HD to SD/3G or incoming signal is not available.

  • Significant Observation
  1. Keep sending the 3G or SD signal to receiver during power up.
  2. Ensure the 3G or SD signal is locked properly.
  3. Switch the incoming signal to HD
  4. Locking issue happened
  • Ensure the reconfig process is written correctly.

- Replacing the reconfig logic files (sdi_ii_ed_reconfig_mgmt & sdi_ii_reconfig_logic) from Altera reference design. (located in submodules folder) or

- Signal tap

  • Ensure start reconfiguration is asserted when reconfiguration required.
  • Ensure reconfig done is asserted after reconfiguration process.
  • Ensure reconfig data are sent correct for HD or SD/3G mode. (refer to sdi_ii_reconfig_logic.v inside the submodules folder).

Debug Steps – SDI II Rx Transceiver

  • Confirm all the transceiver signals are correct. Verify rx_parallel_data, rx_clkout, rx_pll_locked, rx_analogreset, rx_digitalreset, pll_powerdown. (you can found the signal by typing *phy|<signal name> into signal tap).

- Ensure all resets are released.

- Ensure mgmt_clk_clk, rx_clkout, and rx_parallel_data are available.

- Ensure LTD and LTR behaved correctly.

  • LTD asserted : HD and 3G received.
  • LTR asserted : SD received.

Signal Tap - SDI II Rx Transceiver

  • rx_clkout might be same frequency and same phase with reference clock. If the signal tap clock triggered is reference clock, it will shows constant low or constant high.

- You may use rx_clkout as triggered clock to confirm the availability of the clock.

Version history
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Last update:
‎06-26-2019 11:48 PM
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