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Simpler Chaining DMA Testbench Example

Simpler Chaining DMA Testbench Example



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Overview

This article details how to instantiate the Stratix V Hard IP for PCI Express design files, as well as modified design files that allow the user greater control over the configuration of the Root Port and End Point. It will be useful to those wanting to see the configuration process in more detail. The only simulator that the files in this article have been verified to work with is ModelSim.

Important Info

  • Note that the changes recommended in this wiki article are difficult to reverse so make sure that you understand completely the steps taken, or you are sure that you want to permanently change the default testbench.
  • It is generally good practice to delete the "libraries" folder located within the "mentor" folder before compiling design files. If not done, the compiler may not recognize some changes that have been made since the last compilation.
  • For a detailed walkthrough on how to instantiate the Hard IP for PCI Express in Stratix V devices, please see the wiki article The Stratix V Hard IP for PCI Express User Guide Revision 12.01


Gen 1 

Directions To Instantiate The Simpler Testbench Design Files

Before completing the following steps, make sure that you have generated the necessary design files by following the steps outlined in The Stratix V Hard IP for PCI Express User Guide Revision 12.01. These steps are briefly outlined here:

  1. Create a folder to use as the project directory.
  2. Open Qsys within Quartus II.
  3. In Qsys go to File > Open and choose the .qsys file for the PCIe configuration you want (for example: pcie_de_gen1_x4_ast64.qsys)
  4. Navigate to the "Generation" Tab at the top of the Qsys GUI. Choose your preferred HDL language for the Simulation and Testbench Model, and choose "Standard BFMs for Standard Avalon Interfaces" for the Testbench Qsys System. Choose your project folder for the output directory and click "Generate."


After completing these steps you will have created an output directory for the files generated by either Qsys or the Megawizard, and in this directory should be 3 folders (Simulation, Testbench, and Synthesis).

There are 2 files that you will need to succesfully modify the design:

altpcietb_bfm_configure.v

altpcietb_bfm_driver_chaining.v

  • They can be found in this zip file. 
  • Warning: By performing these steps you will be replacing altpcietb_bfm_configure.v and altcpietb_bfm_driver_chaining.v .


  1.   Copy and replace the altpcietb_bfm_driver_chaining.v and altpcietb_bfm_configure.v into the following directory: <project_dir>\testbench\pcie_de_gen1_x?_ast???_tb\simulation\submodules (Note: the pcie_de_gen1_x?_ast???_tb portion is decided by which PCIe configuration you are testing.)
  2. Open up the msim_setup.tcl located in the following directory with an appropriate text editor (Quartus II will work fine): <project_dir>\testbench\mentor
  3.  add "+TEST_NAME = NORMAL" to the .tcl, after the vsim command in the alias elab_debug option. You can also replace NORMAL with FULL or SIMPLE (see the next section). Use this .Tcl  as a reference only.


Directions to Compile and Run the Simpler Testbench Design File

Set the level of the test by opening msim_setup.tcl in a text editor, and changing the value of +TEST_NAME in the elab_debug alias to either "FULL" or "SIMPLE" or "NORMAL". 

Note that the default setting (and original setting before any of the modifications outlined in this article) is NORMAL. You can always run the un-modified version of the design example by setting +TEST_NAME = NORMAL.

NORMAL

  1. Sets up the Root Port and End Point configuration spaces.
  2.  Performs DMA reads and writes and compares the results to check for errors.
  • To view an example of a transcript of the simulation results for the "NORMAL" test case, open this text file in notepad++.

FULL

  1. Sets up the Root Port and End Point configuration spaces. 
  2. Performs 10 downstream memory writes to a given address and 10 downstream memory reads from the same address and compares the results to make sure that they match. page 236 of the user guide in the "References" section for more information.
  • To view an example of a transcript of the simulation results for the "FULL" test case, open this text file   in notepad++.

SIMPLE

  1. Sets up the Root Port and End Point configuration spaces - elaborting on the process, in particular detailing how the BARs are sized. The verbose option of the ebfm_cfg_rp_ep function is set to 1 in this case, which enables readouts detailing the configuration process.
  2.  Perform several configuration register reads :

          a) Reads the contents of the Link Capabilities Register

          b) Reads the contents of the Link Status Register

           c) Reads the contents of the Link Control Register

          d) Writes a 1 to the retrain link bit (bit 5) of the Link Control Register

   3.   Performs 1 downstream memory write to a given address and 1 downstream memory read from the same address and compares the results to make sure that they match.

  • To view an example of a transcript of the simulation results for the "SIMPLE" test case, open this text file in notepad++.


  1. To compile the design, navigate to the directory that contains the .tcl script used to compile the design (<project_dir>\testbench\mentor) using the command prompt in Modelsim (If you cannot see the command prompt window, go to View > Transcript).
  2. use "source msim_setup.tcl" to source the compilation script. You will be provided with a number of compilation routine options.
  3. use "ld_debug" to compile the design.
  4. wait until compilation completes
  5. type "run -all" to run the simulation.


Relevant readouts should appear in the command prompt.


Gen 2 

Directions To Instantiate The Simpler Testbench Design Files

Before completing the following steps, make sure that you have generated the necessary design files by following the steps outlined in The Stratix V Hard IP for PCI Express User Guide Revision 12.01

These steps are briefly outlined here:

  1. Create a folder to use as the project directory.
  2. Open Qsys within Quartus II.
  3. In Qsys go to File > Open and choose the .qsys file for the PCIe configuration you want (for example: pcie_de_gen2_x8_ast256.qsys)
  4. Navigate to the "Generation" Tab at the top of the Qsys GUI. Choose your preferred HDL language for the Simulation and Testbench Model, and choose "Standard BFMs for Standard Avalon Interfaces" for the Testbench Qsys System. Choose your project folder for the output directory and click "Generate."


After completing these steps you will have created an output directory for the files generated by either Qsys or the Megawizard, and in this directory should be 3 folders (Simulation, Testbench, and Synthesis).


There are 4 files that you will need:


altpcietb_bfm_driver_downstream.v

altpcietb_bfm_driver_downstream_main.v

altpcietb_bfm_configure.v

altpcietb_bfm_top_rp.v


  • They can be found in  this zip file.
  • Note: By performing these steps, you will be replacing    altpcietb_bfm_configure.v  and   altpcietb_bfm_driver_downstream.v   and  altpcietb_bfm_top_rp.v  Make sure that you want to replace these files before continuing with these steps.


  1. Place the altpcietb_bfm_driver_downstream.valtpcietb_bfm_driver_downstream_main.valtpcietb_bfm_top_rp.v, and altpcietb_bfm_configure.v  into the following directory: <project_dir>\testbench\pcie_de_gen2_x?_ast???_tb\simulation\submodules (Note: the pcie_de_gen2_x?_ast???_tb portion is decided by which PCIe configuration you are testing.) 
  2. Open up the msim_setup.tcl located in the following directory with an appropriate text editor (Quartus II will work fine):
  3. <project_dir>\testbench\mentor
  4. Perform a find and replace to change "altpcietb_bfm_driver_downstream.v"  to  "altpcietb_bfm_driver_downstream_main.v" within the .tcl
  5. add "+TEST_NAME = FULL" to the .tcl, after the vsim command in the alias elab_debug option. You can also replace FULL with SIMPLE (see the next section).


Directions to Compile and Run the Simpler Testbench Design File

Set the level of the test by opening msim_setup.tcl in a text editor, and changing the value of +TEST_NAME in the elab_debug alias to either "FULL" or "SIMPLE". 

Note that the default setting (and original setting before any of the modifications outlined in this article) is FULL.You can always run the un-modified version of the design example by setting +TEST_NAME = FULL. 

the "NORMAL" mode is not supported with Gen 2, however "FULL" mode is very similiar to "NORMAL."

FULL

  1. Sets up the Root Port and End Point configuration spaces.
  2. Performs 10 downstream memory writes to a given address and 10 downstream memory reads from the same address and compares the results to make sure that they match. 

 See page 236 of the user guide in the "References" section for more information.

  • To view an example of a transcript of the simulation results for the "FULL" test case, open this text file  in notepad++.

SIMPLE

  1. Sets up the Root Port and End Point configuration spaces - elaborting on the process, in particular detailing how the BARs are sized. The verbose option of the ebfm_cfg_rp_ep function is set to 1 in this case, which enables readouts detailing the configuration process. .
  2. Perform several configuration register reads :

       a) Reads the contents of the Link Capabilities Register

       b) Reads the contents of the Link Status Register

       c) Reads the contents of the Link Control Register

       d) Writes a 1 to the retrain link bit (bit 5) of the Link Control Register

   3.  Performs 1 downstream memory write to a given address and 1 downstream memory read from the same address and compares the results to make sure that they match.

  • To view an example of a transcript of the simulation results for the "SIMPLE" test case, open this text file  in notepad++.

  1. To compile the design, navigate to the directory that contains the .tcl script used to compile the design (<project_dir>\testbench\mentor) using the command prompt in Modelsim (If you cannot see the command prompt window, go to View > Transcript).
  2. type "do msim_setup.tcl" to compile the design. You will be provided with a number of compilation routine options.
  3. type "ld_debug" and hit the enter key.
  4. wait until compilation completes
  5. type "run -all" to run the simulation.


Relevant readouts should appear in the command prompt.

 

 

Gen 3 

Directions To Instantiate The Simpler Testbench Design Files

Before completing the following steps, make sure that you have generated the necessary design files by following the steps outlined in The Stratix V Hard IP for PCI Express User Guide Revision 12.01. These steps are briefly outlined here:

  1. Create a folder to use as the project directory.
  2. Open Qsys within Quartus II.
  3. In Qsys go to File > Open and choose the .qsys file for the PCIe configuration you want (for example: pcie_de_gen3_x8_ast256.qsys)
  4. Navigate to the "Generation" Tab at the top of the Qsys GUI. Choose your preferred HDL language for the Simulation and Testbench Model, and choose "Standard BFMs for Standard Avalon Interfaces" for the Testbench Qsys System. Choose your project folder for the output directory and click "Generate."


After completing these steps you will have created an output directory for the files generated by either Qsys or the Megawizard, and in this directory should be 3 folders (Simulation, Testbench, and Synthesis).

There are 2 files that you will need to succesfully modify the design:

altpcietb_bfm_rp_gen3_x8.v

altpcietb_g3bfm_configure.v

  • They can be found inthis zip file.
  • Note: By performing these steps, you will be replacing altpcietb_bfm_rp_gen3_x8.v and altpcietb_g3bfm_configure.v. Make sure that you want to replace these files before continuing with these steps. 
  1.  Copy and replace the altpcietb_bfm_rp_gen3_x8.v and altpcietb_g3bfm_configure.v into the following directory: <project_dir>\testbench\pcie_de_gen3_x?_ast???_tb\simulation\submodules (Note: the pcie_de_gen3_x?_ast???_tb portion is decided by which PCIe configuration you are testing.)
  2. Open the file called msim_setup.tcl in: <project_dir>\testbench\mentor
  3. Add "+TEST_NAME =NORMAL" to the .tcl, after the vsim command in the alias elab_debug option. You can also replace NORMAL with SIMPLE (see the next section for details on what these settings do). Use this .tcl as a reference only.


Directions to Compile and Run the Simpler Testbench Design File

Set the type of the test by opening msim_setup.tcl in a text editor, and changing the value of +TEST_NAME in the elab_debug alias to either "NORMAL" or "SIMPLE". Note that the default setting (and original setting before any of the modifications outlined in this article) is NORMAL. You can always run the un-modified version of the design example by setting +TEST_NAME = NORMAL.

NORMAL

  1. Sets up the Root Port and End Point configuration spaces.
  2.  Performs DMA reads and writes and compares the results to check for errors.
  • To view an example of a transcript of the simulation results for the "NORMAL" test case, open this text file in notepad++. 

SIMPLE

  1. Sets up the Root Port and End Point configuration spaces - elaborting on the process, in particular detailing how the BARs are sized. The verbose option of the ebfm_cfg_rp_ep function is set to 1 in this case, which enables readouts detailing the configuration process.
  2.  Perform several configuration register reads :

          a) Reads the contents of the Link Capabilities Register

          b) Reads the contents of the Link Status Register

           c) Reads the contents of the Link Control Register

          d) Writes a 1 to the retrain link bit (bit 5) of the Link Control Register

   3.   Performs 1 downstream memory write to a given address and 1 downstream memory read from the same address and compares the results to make sure that they match.

  • To view an example of a transcript of the simulation results for the "SIMPLE" test case, open this text file in notepad++.


  1. To compile the design, navigate to the directory that contains the .tcl script used to compile the design (<project_dir>\testbench\mentor) using the command prompt in Modelsim (If you cannot see the command prompt window, go to View > Transcript).
  2. use "source msim_setup.tcl" to source the compilation script. You will be provided with a number of compilation routine options.
  3. use "ld_debug" to compile the design.
  4. wait until compilation completes
  5. type "run -all" to run the simulation.


Relevant readouts should appear in the command prompt.


References

See The Stratix V Hard IP for PCI Express User Guide Revision 12.01for more information.

Disclaimer

© 2011 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not

supported by Altera Corporation. Use the material in this document at your own risk; it might be, for example, objectionable,

misleading or inaccurate.

Key Words

PCIe, PCI E, PCI Express, Stratix V, Simpler testbench DMA chaining design example , Tranceiver Reconfiguration Controller, Stratix V GX, Stratix V GT, SV, SVGX, SVGT, S5GX, S5GT, S5, Stratix 5, Stratix 5 GX, StratixV, StratixV GX, Stratix5, Stratix5 GX

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‎06-26-2019 09:31 PM
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