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SocBootFromFPGA

SocBootFromFPGA


Introduction

The HPS (Hardened Processor System) from the Altera Cyclone V and Arria V SoCs supports several different boot scenarios:

  • Boot from SD/MMC card,
  • Boot from QSPI,
  • Boot from NAND,
  • RAM Boot - on Warm Reset only,
  • Boot from FPGA,
  • FPGA Fallback boot.

This page presents a complete example of how to boot from FPGA on a Cyclone V SoC Development Kit.

For more information about booting refer to Booting and Configuration chapters from:

Prerequisites

The following are required in order to compile and run this example:

  • Host PC running Windows 7 (Linux will also work),
  • Altera Cyclone V SoC Development Kit ver D or newer,
  • Altera Quartus II v14.0 or newer,
  • Altera SoC EDS v14.0 or newer.

Overview

In order to achieve booting from FPGA the following are required:

  • BSEL needs to be set to 0x1 - Boot from FPGA
  • FPGA image needs to have an on-chip memory instantiated, mapped at offset 0x0 behind the HPS2FPGA bridge. The memory needs to be loaded with Preloader executable binary.
  • FPGA image needs to drive the value of the following two signals to HPS, since they are required by BootROM:
    • f2h_boot_from_fpga_ready - indicates that the BootROM can boot from FPGA if BSEL = 0x1
    • f2h_boot_from_fpga_on_failure - indicates that the BootROM can boot from FPGA as a fallback, if it failed booting from the selected BSEL.
  • Preloader executable .text section needs to be linked to address 0xC000_0000 (equivalent of offset 0x0 behind the HPS2FPGA bridge)
  • Preloader executable .data sections need to be linked to address 0xFFFF_0000 (the HPS OCRAM)

Boot Flow

The following picture presents the boot flow used for this example: d/dd/Boot_fpga_overview.png


Note that the Preloader is executed directly from the FPGA memory, while the bare-metal is first copied from the SD/MMC to SDRAM then executed.

It is possible to also store the bare-metal application in the FPGA image, but that memory is expensive and its usage should be minimized.

The bare-metal application is very simple, it just prints the message "Hello World" to confirm that the boot process executed correctly.

FPGA Build Flow

The complete flow for creating the appropriate FPGA image is described in the following diagram: f/fc/Boot_fpga_flow.png


Note that the design needs to be compiled two times:

  • First in order to obtain the handoff folder, which is used to generate the Preloader.
  • Then, after the Preloader hex file is obtained you can update the on chip ram from Quartus: you can either do a full recompile or run the update memory initialization file (see below)

Processing->Update Memory Initialization File

This will update the programming/sof file with the new hex file information for the on chip ram.

This is a handy way to update software for nios as well without doing a full recompile.

Hardware Design

The hardware design is provided as an attachment to this page. It was derived from the GHRD provided with SoC EDS 14.0 with the following modifications:

  • The HPS component was changed to enable boot from FPGA signals
  • The FPGA On-Chip memory data width was reduced from 64bit to 8bit
  • The FPGA On-Chip memory was changed to be initialized with the hex file software/spl_bsp/preloader.hex
  • The top level Verilog file was changed to tie off the HPS boot from FPGA signals accordingly.

The complete instructions for deriving the current design from the GHRD are:

1. Unzip the provided file cv_soc_devkit_boot_fpga.tgz

2. Start Quartus II, and open the project file cv_soc_devkit_boot_fpga/soc_system.qpf

3. From Quartus II, open Qsys and load the file cv_soc_devkit_boot_fpga/soc_system.qsys

4. In Qsys, click on the HPS component and check thee "Enable boot from FPGA signals" box.

b/bd/Enable_boot_fpga_signals.png

5. In Qsys, click on the FPGA On-Chip Memory, and:

  • Change its "Data Width" to 8bit
  • Check the "Enable non-default initialization file" box
  • Type in the path to the hex initialization file that will be built later: "software/spl_bsp/preloader.hex".

c/cf/Fpga_ocram_boot_fpga.png

6. In Qsys, double-click on the HPS's "f2h_boot_from_fpga" signal to have it exported.

c/c3/Boot_fpga_export.png

7. Generate the system, in Qsys. Exit Qsys.

8. In Quartus, open the top level file cv_soc_devkit_boot_fpga/ghrd_top.v and tie off the boot from FPGA signals:

  • f2h_boot_from_fpga_ready = 1 - indicates that the BootROM can boot from FPGA if BSEL = 0x1
  • f2h_boot_from_fpga_on_failure = 0 - indicates that the BootROM cannot boot from FPGA as a fallback

c/c5/Tie_boot_fpga_signals.png

7. Compile the hardware design, in Quartus. This will generate the handoff folder based on which we will generate the Preloader.

Preloader

This section presents how to:

  • Generate the Preloader based on the hardware design,
  • Compile the Preloader,
  • Convert the Preloader executable to a hex file that can be used to initialize the On-Chip memory in the FPGA fabric.

The required steps are:

1. Open an Embedded Command Shell (on Windows, go to Start -> All Programs -> Altera 14.0 -> SoC EDS -> SoC EDS Embedded Command Shell

2. Start the Preloader Generator by running the command "bsp-editor&".

3. In the Preloader Generator, go to File -> New BSP ... to open the New BSP window.

4. In the New BSP window, browse the Preloader settings directory to point to the handoff folder from the hardware design. Then click OK to close the window.

4/41/Boot_fpga_browse_handoff.png

5. In the Preloader Generator window, perform the following:

  • Uncheck WATCHDOG_ENABLE to disable the watchdog (it is not serviced by the bare-metal application)
  • Check EXE_ON_FPGA. This instructs the Preloader to put the program in the FPGA address space, and use HPS OCRAM for rw data.
  • Check the SDRAM_SCRUBBING and SDRAM_SCRUBBING_REMAIN_REGION. This will clear out the SDRAM before the application is ran
  • Check BOOT_FROM_SDMMC and uncheck the other BOOT_FROM_ options
  • Make note of the SDMMC_NEXT_BOOT_IMAGE, which defaults to 0x40000. This is the offset in the custom partition where the Preloader will get the application image from.

d/d1/Fpga_boot_preloader_settings.png

6. Click Generate in the Preloader Generator window. Then click Exit to close the window.

7. In the Embedded Command Shell, change current folder to the location where the Preloader was generated cv_soc_devkit_boot_fpga/software/spl_bsp

8. In the Embedded Command Shell, run the "make" command to build the Preloader.

9. Run the following command to convert the Preloader ELF file to HEX:

arm-altera-eabi-objcopy -O ihex --adjust-vma -0xc0000000 uboot-socfpga/spl/u-boot-spl preloader.hex

Note that the hardware design needs to now be recompiled or just update the RAM (see below), to make use of the above hex file to initialize the FPGA On-Chip memory used to boot.

Update the on chip ram from Quartus:

Processing->Update Memory Initialization File

This will update the programming/sof file with the new hex file information for the on chip ram.

This is a handy way to update software for nios as well without doing a full recompile.

Bare-metal Application

The bare-metal application simply displays the message "Hello World" over the serial port.

The application can be downloaded from the SoC Examples page at http://www.altera.com/support/examples/soc/soc.html. Select the "Unhosted" example, CV Version.

The direct link is http://www.altera.com/support/examples/soc/Altera-SoCFPGA-HardwareLib-Unhosted-CV-GNU.tar.gz

The application can be imported and built in the ARM DS-5 Altera Edition, or from the Embedded Command Shell prompt by invoking "make". This will create the image file hello-mkimage.bin.

Alternatively, the pre-compiled image is also attached to this page, so that the bare-metal project does not need to be re-compiled.

Running the Example

1. Manually create an SD card with a custom partition with id=A2 using fdisk, or use the example SD card image that comes with SoC EDS:

  • Unzip the SD Card Image provided in the <SoCEDS installation folder>:\embedded\embeddedsw\socfpga\prebuilt_images\sd_card_linux_boot_image.tar.gz by using the command
  • tar -xzf <filename>
  • from the Embedded Command Shell. This will create the file sd_card_linux_boot_image.img’
  • Use the free Win32DiskImager tool to write the file sd_card_linux_boot_image.img to an SD card.

2. Write the Bare-metal application image to the SD card custom partition, using the SD card boot utility that is part of SoC EDS:

  • Start an Embedded Command Shell
  • Run the following command
  • alt-boot-disk-util -a write -b hello-mkimage.bin -d <sd_card_drive_letter>

3. Configure the Cyclone V board to boot from FPGA by setting the BOOTSEL jumpers like this:

  • BOOTSEL0 (J28): left
  • BOOTSEL1 (J29): right
  • BOOTSEL2 (J30): right

4. Connect the board to the PC using the USB serial connection, and start a serial terminal on the PC, using 115,200-8-N-1.

5. Insert the SD card on the board

6. Power up the board. There should be nothing coming from the board on the serial terminal, since the FPGA is not configured, so the Boot ROM will not jump to FPGA yet.

7. Configure the FPGA by using the Quartus Programmer, with the cv_soc_devkit_boot_fpga/output_files/soc_system.sof file.

8. Press the HPS Cold Reset button (S7)

9. The serial console will show the Preloader being run from FPGA, then the bare-metal application being run from the SD card.

f/fe/Boot_fpga_log.png

Files

This example is delivered as an archive: Cv soc devkit boot fpga.zip.

The most relevant files and folders that compose the archive are presented below:

cv_soc_devkit_boot_fpga

output_files

soc_system.sof - Precompiled FPGA image file

software

spl_bsp

preloader.hex - Precompiled Preloader hex file

hello-mkimage.bin - Precompiled bare-metal application

soc_system.qpf - FPGA project file

References

Version history
Revision #:
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Last update:
‎06-26-2019 06:31 PM
Updated by:
 
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