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The HPS (Hardened Processor System) from the Altera Cyclone V and Arria V SoCs supports several different boot scenarios:
This page presents a complete example of how to boot from FPGA on a Cyclone V SoC Development Kit.
For more information about booting refer to Booting and Configuration chapters from:
The following are required in order to compile and run this example:
In order to achieve booting from FPGA the following are required:
The following picture presents the boot flow used for this example: d/dd/Boot_fpga_overview.png
Note that the Preloader is executed directly from the FPGA memory, while the bare-metal is first copied from the SD/MMC to SDRAM then executed.
It is possible to also store the bare-metal application in the FPGA image, but that memory is expensive and its usage should be minimized.
The bare-metal application is very simple, it just prints the message "Hello World" to confirm that the boot process executed correctly.
The complete flow for creating the appropriate FPGA image is described in the following diagram: f/fc/Boot_fpga_flow.png
Note that the design needs to be compiled two times:
Processing->Update Memory Initialization File
This will update the programming/sof file with the new hex file information for the on chip ram.
This is a handy way to update software for nios as well without doing a full recompile.
The hardware design is provided as an attachment to this page. It was derived from the GHRD provided with SoC EDS 14.0 with the following modifications:
The complete instructions for deriving the current design from the GHRD are:
1. Unzip the provided file cv_soc_devkit_boot_fpga.tgz
2. Start Quartus II, and open the project file cv_soc_devkit_boot_fpga/soc_system.qpf
3. From Quartus II, open Qsys and load the file cv_soc_devkit_boot_fpga/soc_system.qsys
4. In Qsys, click on the HPS component and check thee "Enable boot from FPGA signals" box.
b/bd/Enable_boot_fpga_signals.png
5. In Qsys, click on the FPGA On-Chip Memory, and:
6. In Qsys, double-click on the HPS's "f2h_boot_from_fpga" signal to have it exported.
7. Generate the system, in Qsys. Exit Qsys.
8. In Quartus, open the top level file cv_soc_devkit_boot_fpga/ghrd_top.v and tie off the boot from FPGA signals:
c/c5/Tie_boot_fpga_signals.png
7. Compile the hardware design, in Quartus. This will generate the handoff folder based on which we will generate the Preloader.
This section presents how to:
The required steps are:
1. Open an Embedded Command Shell (on Windows, go to Start -> All Programs -> Altera 14.0 -> SoC EDS -> SoC EDS Embedded Command Shell
2. Start the Preloader Generator by running the command "bsp-editor&".
3. In the Preloader Generator, go to File -> New BSP ... to open the New BSP window.
4. In the New BSP window, browse the Preloader settings directory to point to the handoff folder from the hardware design. Then click OK to close the window.
4/41/Boot_fpga_browse_handoff.png
5. In the Preloader Generator window, perform the following:
d/d1/Fpga_boot_preloader_settings.png
6. Click Generate in the Preloader Generator window. Then click Exit to close the window.
7. In the Embedded Command Shell, change current folder to the location where the Preloader was generated cv_soc_devkit_boot_fpga/software/spl_bsp
8. In the Embedded Command Shell, run the "make" command to build the Preloader.
9. Run the following command to convert the Preloader ELF file to HEX:
arm-altera-eabi-objcopy -O ihex --adjust-vma -0xc0000000 uboot-socfpga/spl/u-boot-spl preloader.hex
Note that the hardware design needs to now be recompiled or just update the RAM (see below), to make use of the above hex file to initialize the FPGA On-Chip memory used to boot.
Update the on chip ram from Quartus:
Processing->Update Memory Initialization File
This will update the programming/sof file with the new hex file information for the on chip ram.
This is a handy way to update software for nios as well without doing a full recompile.
The bare-metal application simply displays the message "Hello World" over the serial port.
The application can be downloaded from the SoC Examples page at http://www.altera.com/support/examples/soc/soc.html . Select the "Unhosted" example, CV Version.
The direct link is http://www.altera.com/support/examples/soc/Altera-SoCFPGA-HardwareLib-Unhosted-CV-GNU.tar.gz
The application can be imported and built in the ARM DS-5 Altera Edition, or from the Embedded Command Shell prompt by invoking "make". This will create the image file hello-mkimage.bin.
Alternatively, the pre-compiled image is also attached to this page, so that the bare-metal project does not need to be re-compiled.
1. Manually create an SD card with a custom partition with id=A2 using fdisk, or use the example SD card image that comes with SoC EDS:
2. Write the Bare-metal application image to the SD card custom partition, using the SD card boot utility that is part of SoC EDS:
3. Configure the Cyclone V board to boot from FPGA by setting the BOOTSEL jumpers like this:
4. Connect the board to the PC using the USB serial connection, and start a serial terminal on the PC, using 115,200-8-N-1.
5. Insert the SD card on the board
6. Power up the board. There should be nothing coming from the board on the serial terminal, since the FPGA is not configured, so the Boot ROM will not jump to FPGA yet.
7. Configure the FPGA by using the Quartus Programmer, with the cv_soc_devkit_boot_fpga/output_files/soc_system.sof file.
8. Press the HPS Cold Reset button (S7)
9. The serial console will show the Preloader being run from FPGA, then the bare-metal application being run from the SD card.
This example is delivered as an archive: Cv soc devkit boot fpga.zip.
The most relevant files and folders that compose the archive are presented below:
cv_soc_devkit_boot_fpga
output_files
soc_system.sof - Precompiled FPGA image file
software
spl_bsp
preloader.hex - Precompiled Preloader hex file
hello-mkimage.bin - Precompiled bare-metal application
soc_system.qpf - FPGA project file
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