In transceiver Basic mode, Rate match FIFO is used to compensate the clock frequency difference between local CDR recovered clock and upstream transmitter clock by insert and delete the special rate match characters.Rate match FIFO can compensate for small clock frequency up to +/- 300PPM.
Mostly of the users thought that the hard rate match FIFO's deletion/insertion method for Transceiver Basic mode is same as Transceiver GIGE mode. However, this is totally wrong because in Basic mode, the deletion/insertion was based on /K-S/ ordered set. A /K-S/ ordered set is defined as a /K/ followed by a consecutive number of /S/ (KSSS).The symbols inserted/deleted are /S/ only.Besides that, when rate match FIFO's full signal was asserted, the rate match FIFO will automatic delete the data byte that cause the FIFO to go full. For further info on how transceiver rate match FIFO perform deletion/insertion in Basic mode, please refer to Altera Device Handbook Vol.2, Transceiver Functional Modes chapter.
Below diagram show how the deletion,insertion,FIFO full condition happen in Basic mode.
Both dev kit's reference clock is synchronized.This will ease for control the PPM difference between local CDR recovered clock and upstream transmitter clock. The pattern sequence been used is …IPG->DATA->IPG->DATA…, Where IPG= BC50, DATA=55AA. By just increased 10PPM at TX side, we can observe the result via SignalTap. Capture the signal at the RX through SignalTap.