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Source Synchronous Analysis with TimeQuest

Source Synchronous Analysis with TimeQuest



Source Synchronous Timing.pdf

Source Synchronous Timing Projects.zip

This document goes into detail on how to constrain source-synchronous interfaces. It is a follow-on to the TimeQuest User Guide:

https://forums.intel.com/s/createarticlepage?articleid=a3g0P0000005R9MQAU&action=view

The document starts off with a standardized approach to constraining source-synchronous interfaces, called the Explicit Clock Method.  This easy-to-understand method works whether the FPGA is the receiver or transmitter, and if the interfaces are center-aligned or edge-aligned.  

Next is a section on the Implicit Clock Method, which I consider to be purely optional. 

There is a section called Miscellaneous, which covers many of the details and points of confusion for source-synchronous DDR interfaces. 

Finally are the examples. There are some generic examples(without projects) as well as analysis of four Texas Instrument devices interfacing to an FPGA. 


I started a thread on this document in the alteraforum at:

http://www.alteraforum.com/forum/showthread.php?p=128042#post128042

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Last update:
‎06-26-2019 06:35 PM
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