To read or write Avalon Memory-Mapped (Avalon-MM) slaves using special masters
To sample the SOPC system clock as well as system reset signal
To run JTAG loopback tests to analyze board noise problems
To shift arbitrary instruction register and data register values to instantiated system level debug (SLD) nodes
System Console is intended as a low level tool for tasks such as board bring up and device driver debugging. System Console along with SOPC Builder provides the framework and baseline functionality that you need to compose your own sophisticated instrumentation and verification solution.
While System Console provides the low level TCL commands, a lot of useful and powerful functionality can be derived from stringing a series of commands together. Since System Console is a full fledged TCL interpreter, these can be saved as TCL Macros in file, and then the file can be sourced in the shell and used.
Please share your TCL Macros here and extend System Console's capabilties.
Default master - Simplified memory access commands for systems with only one memory master
Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.
Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.