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This guide demonstrates several ways to add automatic build identification to your projects using Tcl scripts. The two scripts presented in this guide create either a Verilog module or a Memory Initialization File (MIF) that contains a timestamp, the host name, and the physical address from your machine at compilation time. These scripts can be run manually or can be executed automatically each time you compile your design.
This guide assumes that you have prior experience using Quartus II as well as some familiarity with Verilog and Tcl. To run the scripts presented in this guide, you must have the following software installed:
Two Tcl scripts are provided with this guide in the build_identification.zip file: the Build ID Verilog Module Script (build_id_verilog.tcl) and the Build ID Memory Initialization File Script (build_id_mif.tcl).
The build_id_verilog.tcl script generates a Verilog file (build_id.v) with a module (build_id) that contains a timestamp, physical address, and host name for the current build. These values are available from the build_date, build_time, physical_address, and host_name output ports of the build_id module in the build_id.v Verilog source file.
The format for each value is as follows:
The follow code is an example output of the build_id_verilog.tcl script:
// Build ID Verilog Module
//
// Date: 08012011
// Time: 083920
// Physical Address: 12-34-56-78-9A-BC
// Host Name: MY-COMPUTER
module build_id
(
output [31:0] build_date,
output [31:0] build_time,
output [47:0] physical_address,
output [119:0] host_name
);
assign project_date = 32'd08012011;
assign project_time = 32'd083920;
assign physical_address = 48'h123456789ABC;
assign host_name = 120'h000000004d592d434f4d5055544552;
endmodule
The build_id_mif.tcl script generates a Memory Initialization File (build_id.mif) that contains a timestamp, physical address, and host name for the current build. The address range and format for each value is as follows:
The follow code is an example output of the build_id_mif.tcl script:
-- Build ID Memory Initialization File
--
-- Date: 08012011
-- Time: 083920
-- Physical Address: 12-34-56-78-9A-BC
-- Host Name: MY-COMPUTER
DEPTH = 28
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT
BEGIN
-- Build Date
000 : 00;
001 : 7A;
002 : 40;
003 : EB;
-- Build Time
004 : 00;
005 : 01;
006 : 47;
007 : D0;
-- Physical Address
008 : 00;
009 : 00;
00a : 12;
00b : 34;
00c : 56;
00d : 78;
00e : 9A;
00f : BC;
-- Host Name
010 : 4D;
011 : 59;
012 : 2D;
013 : 43;
014 : 4F;
015 : 4D;
016 : 50;
017 : 55;
018 : 54;
019 : 45;
01a : 52;
01b : 00;
END;
Both scripts can be run manually through theTcl Console in Quartus or can be added to the compilation flow to run automatically with each build.
Figure 1 – Running the Build ID Memory Initialization Script in the Tcl Console 6/67/Running_the_Build_ID_script.png
After the script has finished running, a confirmation message will be displayed in the Messages Window, shown in Figure 2. If the Messages Window is not visible, open it by selecting View > Utility Windows > Messages or by pressing Alt + 3.
Figure 2 – Confirmation message from the Build ID Memory Initialization Script 3/3b/Build_ID_confirmation.png
These commands tell Quartus to automatically run the selected script before each compilation. The Verilog module or Memory Initialization File will be regenerated every time you compile your design.
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