Transceiver Design Flow Level 2 - The Avalon MM Master
Overview
This Level 2 article serves to guide the user through the creation, instantiation, connection, and use of an Avalon MM Master as a part of a complete transceiver design. This article is a part of the complete Transceiver Design Flow series of articles.
Required Materials
Documentation
- Stratix V Documentation - Use this for information on Stratix V device architecture.
- Transceiver Configurations in Stratix V Devices - Provides the transceiver channel datapath, clocking guidelines, channel placement guidelines, and a brief description of protocol features supported in each transceiver configuration for Stratix V devices.
- Altera Transceiver PHY IP Core User Guide - Provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera PHY IP core. The Altera IP Library is installed as part of
- the Quartus II installation process. You can select and parameterize any Altera IP core from the library using the MegaWizard in Quartus II.
- Avalon Specification - This document defines interfaces appropriate for streaming high-speed data, reading and writing registers and memory, and controlling off-chip devices.
What Is It?
Avalon Memory-Mapped (Avalon-MM) Masters are used to talk to
1) Talk to the Transceiver PHY IP in order to write to/read from the control and status registers. For more information see the chapter that corresponds to the specific PHY you are implementing in the User Guide.
2) Talk to the Reconfiguration Controller in order to write to /read from the reconfiguration control space within the Transceiver PHY IP. For a PHY Layer Transceiver Design, the Avalon MM Master controls the Reconfiguration Controller through the Reconfiguration Management Interface.
For technical details about the Avalon MM Interface including signals and timing diagrams, see Chapter 3 of the Avalon Specification.
Creating an Avalon MM Master
The Avalon MM Master can be a user module, or a microcontroller. Communication between it's slave however must follow the Avalon MM Specification.
See this template for a reference for using a user coded module.
Key Words
Stratix V, PCIE PIPE PHY IP, Tranceiver Reconfiguration Controller, Physical layer, PCI Express, Express, Stratix Five, GT, GS, GX, Design, Example, guide, walkthrough,
PCIe, PCI E, PCI Express, Stratix V, SV, S, V, Walkthrough, guide, help, Stratix V GX, Stratix V GT, SV, SVGX, SVGT, S5GX, S5GT, S5, Stratix 5, Stratix 5 GX, StratixV, StratixV GX, Stratix5, Stratix5 GX, Altera, generated, generation, Instantiation, creation, design, files, Avalon, MM, Memory, mapped, Master, interface
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