This Level 2 article serves to guide the user through the creation, instantiation, connection, and use of an Avalon MM Master as a part of a complete transceiver design. This article is a part of the complete Transceiver Design Flow series of articles.
Avalon Memory-Mapped (Avalon-MM) Masters are used to talk to
1) Talk to the Transceiver PHY IP in order to write to/read from the control and status registers. For more information see the chapter that corresponds to the specific PHY you are implementing in the User Guide.
2) Talk to the Reconfiguration Controller in order to write to /read from the reconfiguration control space within the Transceiver PHY IP. For a PHY Layer Transceiver Design, the Avalon MM Master controls the Reconfiguration Controller through the Reconfiguration Management Interface.
For technical details about the Avalon MM Interface including signals and timing diagrams, see Chapter 3 of the Avalon Specification.
The Avalon MM Master can be a user module, or a microcontroller. Communication between it's slave however must follow the Avalon MM Specification.
See this template for a reference for using a user coded module.
Stratix V, PCIE PIPE PHY IP, Tranceiver Reconfiguration Controller, Physical layer, PCI Express, Express, Stratix Five, GT, GS, GX, Design, Example, guide, walkthrough,
PCIe, PCI E, PCI Express, Stratix V, SV, S, V, Walkthrough, guide, help, Stratix V GX, Stratix V GT, SV, SVGX, SVGT, S5GX, S5GT, S5, Stratix 5, Stratix 5 GX, StratixV, StratixV GX, Stratix5, Stratix5 GX, Altera, generated, generation, Instantiation, creation, design, files, Avalon, MM, Memory, mapped, Master, interface
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