Transceiver Design Flow Level 2 - Writing a Transceiver Compilation Script

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Transceiver Design Flow Level 2 - Writing a Transceiver Compilation Script (.Tcl)

Overview

This Level 2 article guides the user through understanding and writing a compilation. Tcl for ModelSim as a part of a complete transceiver design. This article is a part of the complete Transceiver Design Flow series of articles.

Required Materials

• Modelsim 10.0d Understanding of the information contained in Transceiver Design Flow Level 1.

Documentation

• Stratix® V Documentation - Use this for information on Stratix V device architecture.
• Transceiver Configurations in Stratix V Devices - Provides the transceiver channel datapath, clocking guidelines, channel placement guidelines, and a brief description of protocol features supported in each transceiver configuration for Stratix V devices.
• V-Series Transceiver PHY IP Core User Guide   - Provides a general overview of the Altera IP core design flow to help you quickly get started with any Altera PHY IP core. The Altera IP Library is installed as part of
• the Quartus II installation process. You can select and parameterize any Altera IP core from the library using the MegaWizard in Quartus II.
• Avalon Specification - This document defines interfaces appropriate for streaming high-speed data, reading and writing registers and memory, and controlling off-chip devices.

Transceiver Design Compilation .Tcl

You will need to create a .tcl script called phy_sim_top.tcl that contains compilation commands for:

1. Setting the root directory as well as setting the simulator
2. Stratix V Simulation Models
3. Transceiver PHY IP Instance files
4. Reconfig Controller instance files
5. (Possibly Reset Controller Instance Files depending on whether the reset controller is external to the Transceiver PHY IP or not)
6. User created design files
7. The Top Level Testbench file
8. Commands to invoke the simulator

Setting the Root Directory / Simulator

it will be useful to create a variable called QUARTUS_ROOTDIR and set it equal to your specific quartus root directory. This is because the root directory path name is used in the compilation of Stratix V Simulation Models. 

set QUARTUS_ROOTDIR <root_directory>

Stratix V Simulation Models

Stratix V Simulation Models files require their own library. Create a new library (a library is just a directory to place the results (proprietary Mentor files) that result from compiling a design file) by using the command

vlib <library_name>

Then compile each Stratix V Simulation Model into the Library that you created by using the command

vlog -work <library_name> -sv $QUARTUS_ROOTDIR/eda/sim_lib/<sim_model>.sv

The vlog command is the Modelsim compilation command. It is used as such: vlog <option-1> <option-2> <option-n...> <file_path_and_name>. 

The -work option specifies (unintuitively) that the compilation result will be placed into the library called <library_name> 

The -sv option specifies that this file is a SystemVerilog file. Do not use this option if the file is a Verilog file.

Transceiver PHY IP Instance Files

These design files require their own library. Use the vsim command to create a library and then use vlog -work <library_name> <file_name> to compile each design file in the PHY IP. It is critical that you compile the ifles in the order given in the plain_files.txt file that is located in the Transceiver's PHY IP "_sim" folder.

Reconfiguration Controller Instance Files

These design files require their own library. Use the vsim command to create a library and then use vlog -work <library_name> <file_name> to compile each design file in the PHY IP. It is critical that you compile the ifles in the order given in the plain_files.txt file that is located in the Reconfiguration Controller's PHY IP "_sim" folder.

Reset Controller (Depending on the Transceiver PHY IP Implemented)

These design files require their own library. Use the vsim command to create a library and then use vlog -work <library_name> <file_name> to compile each design file in the PHY IP. It is critical that you compile the ifles in the order given in the plain_files.txt file that is located in the Reconfiguration Controller's PHY IP "_sim" folder.

User Created Design Files

User created deisgn files can be compiled into the default wiork file, so the -work option is not neded. 

Top level Testbench

This file is compiled exactly like the user created design files.

Commands to Invoke the Simulator

User the vsim command to invoke the simulator.

The -c option runs the simulator in command line mode. 

The -novopt option resovles certain compatibility issues. 

The -t <time> (for example -t 1ps) option sets the timescale used. 

The -L <library_name> lets the simulator know where to look for compilation results. Make sure that you have a -L <library_name> option for each library that you created.

Reference Script

Use this compilation .Tcl script as a reference.

Level 3 - Writing Your Own Compilation Script

Please see the Level 3 Article - Writing Your Own ModelSim Compilation Script, for an advanced guide to writing compilation scripts for ModelSim.

Key Words

Stratix V, PCIE PIPE PHY IP, Tranceiver Reconfiguration Controller, Physical layer, PCI Express, Express, Stratix Five, GT, GS, GX, Design, Example, guide, walkthrough,

PCIe, PCI E, PCI Express, Stratix V, SV, S, V, Walkthrough, guide, help, Stratix V GX, Stratix V GT, SV, SVGX, SVGT, S5GX, S5GT, S5, Stratix 5, Stratix 5 GX, StratixV, StratixV GX, Stratix5, Stratix5 GX, Altera, generated, generation, Instantiation, creation, design, files,

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