December 22, 2010
The purpose of this reference design is for hardware testing without using Nios II processor or any others Memory Map driver to configure TSE. This reference design is using System Console to replace Nios II processor and emulate how the processor will work in SOPC system to configure TSE. System Console can be used on all hardware with a JTAG connector and configurations through System Console is very dynamic.
This reference design is targeted for software designer who wish understand the TSE configuration flow for various configuration modes and thus ease them in creating the configuration program and also hardware designer who lack of programming skill to write a C++ programming for Nios II processor to do hardware testing without any software.
System Console: Interactive console for low-level system debug of SOPC Builder-based systems over JTAG. Based on Tcl, it has a simple set of commands for communicating with various parts of your SOPC Builder system.
Tcl Script: Tool Command Language Script.
Stratix IV GX FPGA Development Kit: Dev Kit used for this design example.
JTAG Interface: Interface between hardware and System Console.
Stratix IV GX FPGA: FPGA on Dev Kit used for this design example.
JTAG Controller: Built in controller in FPGA.
SOPC Builder System: Powerful system development tool that enables you to define and generate a complete system-on-a-programmable-chip (SOPC) in much less time than using traditional, manual integration methods.
JTAG Master: Provide a connection between host systems and SOPC Builder systems via physical interfaces. Host systems can initiate Avalon Memory-Mapped transactions by sending encoded streams of bytes via the cores’ physical interfaces.
System Interconnect Fabric: high-bandwidth interconnect structure for connecting components that use the Avalon® Memory-Mapped (Avalon-MM) interface.
Ethernet Packet Generator: SOPC custom component created using the component editor. It has an Avalon Memory-Mapped (Avalon-MM) slave interface on one side for control purposes and an Avalon-ST source interface on the other side for sending Ethernet packets to the TSE MegaCore function. This block drives the TSE MegaCore function Transmit FIFO interface by generating a stream of Ethernet packets into it.
Ethernet Packet Monitor: SOPC custom component created using the component editor. It has an Avalon-MM slave interface on one side for control purposes and an Avalon-ST sink interface on the other side for the data path. This block is fed a stream of Ethernet packets by the TSE MegaCore function Receive FIFO interface. The Ethernet Packet Monitor also verifies the accuracy of the received payload.
Error Adapter: Ensures that per-bit error information provided by the source interface is correctly connected to the sink interface’s input error signal. Matching error conditions handled by the source and sink are connected. If the source has an error condition that is not supported by the sink, the signal is left unconnected. It can support TSE's Avalon ST data bus with 32-bits data width. It is used for Avalon ST TX to Avalon ST RX reverse loopback purpose. It is needed since ff_tx_err is only 1-bit signal while rx_err is 6-bits signals.
ST MUX: SOPC custom component created using the component editor. It has an Avalon Memory-Mapped (Avalon-MM) slave interface on one side for control purposes, two Avalon-ST sink interfaces on the other side, one of the sink is connected to the source of Ethernet Packet Generator for forward loopback purpose while the other sink is connected to the source of Error Adapter for reverse loopback purpose and an Avalon-ST source interface on the other side for sending Ethernet packets to the TSE MegaCore function.
ASO Splitter: SOPC custom component created using the component editor. It has an Avalon-ST sink interface on one side for receiving Ethernet packets from the TSE MegaCore function and two Avalon-ST source interfaces on the other side, one of the source is connected to the sink of Ethernet Packet Monitor for forward loopback purpose while the other source is connected to the sink of Error Adapter for reverse loopback purpose.
TSE MegaCore: MAC with MII/GMII interface variant is used in this reference design.
2-to-1 MUX: Multiplexer to choose either MII interface for 10/100Mbps speed rate or GMII interface for 1Gbps speed rate.
10/100/1000 Quad-PHY HSMC Daughter Card: The MorethanIP PhyworkX Quad-PHY Ethernet Development Kit provides an Ethernet PHY Daughter Card enabling triple-speed 10/100/1000 Ethernet copper connectivity using 4 standard RJ45 connectors. It implements a High Speed Mezzanine Card (HSMC) connector to the Dev Kit that implements parallel (MII/GMII, RGMII) and serial interfaces (SGMII).
88E1145 PHY: High Performance Marvell 10/100/1000 Quad Ethernet PHY.
External Ethernet Packet Generator: Any industrial standard Ethernet Packet Generator that can generate packets in 10/100/1000Mbps.
This reference design can be tested in 2 methods:
1. In order to run reverse loopback (Avalon ST TX to Avalon ST RX) test, user must connect the hardware to External Ethernet Packet Generator.
2. Download s4gx_mii_gmii.qar file from the link below and extract the archive file by using Quartus II 10.1 software.
3. Open Quartus II programmer and configure Stratix IV GX FPGA Development Kit with top.sof configuration image file.
4. Open SOPC Builder, click on "Tools" option then click "System Console" to open System Console's window.
5. Change the directory to a folder name "sc_tcl" by key in command below on System Console follow by "Enter" key.
6. User may open config.tcl script by using any text editor. This Tcl script is for MAC and PHY configuration settings. Parameter that can be set are COMMAND_CONFIG, FIFO threshold and etc. for MAC and PHY's speed and duplex mode for PHY. 1. After user have set the configuration setting, key in command below on System Console follow by "Enter" key.
7. Observe the message shown on System Console, check if the configuration is correct and it will show if the copper link is established or not with which speed and duplex mode.
8. Start the packet generation by using External Ethernet Packet Generator. Once the transmission is done observe the result on External Ethernet Packet Generator to check if the packets loopback to the External Ethernet Packet Generator is valid or not.
9. In order to monitor the internal Statistics Counters of TSE, key in command below on System Console follow by "Enter" key.
10. The value of each Statistics Counters will be shown on System Console.
1. In order to run forward loopback (Local MAC Loopback) test, user do not require any External Ethernet Packet Generator. Dev kit does not need to connect to any external device.
2. Follow the same steps from step 2 to step 7 shown in reverse loopback test to configure the dev kit.
3. Please set LOOP_ENA parameter in config.tcl to 1 when running a Local MAC loopback test.
4. User may open eth_gen_start.tcl script by using any text editor. This Tcl script is for Ethernet Packet Generator configuration settings and then start the generator operation. Turn ON Ethernet Packet Generator and set the number of packets, fixed or random length, packet's length if it is fixed length packet, incremental or random pattern and random seed if it is random pattern packet for generator to generate. Set the source address same as destination address for self loopback test.
5. Remember to run the config.tcl first before run eth_gen_start.tcl.
6. Once the eth_gen_start.tcl is executed, the Ethernet Packet Generator will straight away start packet generation.
7. Wait until the Ethernet Packet Monitor finished receiving packets, System Console will show the result of the loopback test.
8. If error occurs, System Console will show how many packets with errors and what types of error have occurs.
9. In order to monitor the internal Statistics Counters of TSE, follow the step 9 shown in reverse loopback test.
Extra Note: please don't modify tse_mac_config.tcl, tse_marvel_phy.tcl, eth_gen_mon.tcl and tse_stat_read.tcl unless it is truly necessary. User may study these Tcl scripts to understand flow of TSE's configuration and develop any software to configure TSE by using Nios II processor.
This design was constrained and compile for Quartus II 10.1 for Stratix IV GX FPGA Development Kit with 10/100/1000 Quad-PHY HSMC Daughter Card.
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