Prior to the workshop download, install and load Quartus Prime Lite design software to your laptop. Allow 40+ minutes for the installation process. No license is required.
The materials for each workshop can be found below.
This workshop consists of an hour lecture and 3 hour lab explaining how FPGAs work and the associated design flow using the Quartus development tools. The lab will guide the student through project creation and setup, followed by writing Verilog code for a series of small electronics projects that are programmed on to DE10-Lite FPGA development kit. This course is ideally suited for first and second year EE/CS students familiar with Boolean combinational logic and sequential logic who have written small amounts of code in software languages such as C, Java or Python.
Lab Manual - File:Intro to FPGA Lab Manual.pdf
Lecture Slides - File:Intro to FPGA Workshop Slides.pdf
This workshop consists of an hour lecture and 3 hour lab explaining how to use Intel’s Nios II processor, associated Platform Designer (Qsys) system development tool and Eclipse IDE. Workshop participants will learnt how to assemble a customized embedded system using an FPGA “soft” Nios II processor, peripherals and FPGA fabric. The lab will take participants through all steps from project setup, hardware development, “Bare Metal” embedded software development and downloading the resulting project on the DE10-Lite development kit. This workshop is ideal for people who are familiar with computer architecture and embedded software development in C.
Lab Manual - File:Embedded NIOS Lab Manual.pdf
Lecture Slides - File:Embedded NIOS Workshop Slides.pdf
This workshop consists of a two hour lecture/exercise session followed by a two hour lab training the fundamentals of timing analysis for digital electronics. The student will learn the foundation of timing constraints and how to calculate timing “slack” through a number of paper and pencil exercises to understand how timing margin is calculated. The second portion of this workshop will focus on Intel’s Quartus Timing Analysis tools to give the student hands on knowledge of writing timing constraints, analyzing timing slack, and working on corrective methods to improve timing margin of digital designs implemented in FPGAs.
Lab Manual - File:Timing Analysis Manual.docx
Lecture Slides - File:Timing Analysis Workshop.pptx
This workshop consists of a one hour lecture followed by three hours of laboratory exercises to learn the fundamentals of logic simulation and FPGA debugging tools available in Quartus using the DE10-Lite development kit. The objective of this course is to familiarize students with various debugging tools available in the Quartus FPGA tool suite. The laboratory exercises give the students hands on experience with ModelSim simulation, the SignalTap on-chip logic analyzer, In-system Sources and Probes, as well as the System Console instrumentation suite using the DE10-Lite Development Kit.
Lab Manual - File:Intro to FPGA Simulation Debug Manual.docx
Lecture - File:Intro to FPGA Simulation Debug.pptx
This workshop consists of a 90 minute lecture followed by a 90 minute lab introducing the attendee to high speed serializer/deserializer (SERDES/Transceiver) circuits in digital electronics. High speed I/O SERDES circuits are used in a myriad of interfaces used in digital electronics such as Ethernet, PCI Express, and USB. The workshop will provide background on the fundamentals of how transceiver (SERDES) circuits work and the design flow used for incorporation into an Intel FPGA. The laboratory session guides the student through the process of configuring and assembling a transceiver bidirectional channel, simulating its behavior and confirming its operation on the Cyclone V GX Starter kit.
Lab Manual: File:5cgx xcvr tutorial.docx
Lecture: File:Introduction to FPGA HSIO.pptx
This workshop consists of a one hour lecture followed by a three hour lab introducing the attendee to digital video. A brief history of video distribution and connectivity methods and standards will be followed by a more detailed analysis of VGA hardware. The workshop will introduce the student on how digital video is stored, displayed and formatted on monitors. The student should possess a general knowledge of digital electronics and the Verilog Hardware description language. The lab will highlight VGA timing and control and end with a demonstration/modification of a class Pong game. The laboratory session requires a MAX10 DE10-Lite development kit and a VGA capable monitor plus the Quartus Prime-Lite software.
Lab Manual: File:IntroToVideoUsingFPGAManual.docx
This workshop consists of a one hour lecture followed by a three hour lab introducing the attendee to memory structures used internally and externally with FPGAs. A brief history of digital memory solutions will be followed by an analysis of FPGA memory structures used internally to the FPGA as well as controllers and connectivity from the FPGA to DRAM devices. The student should possess a general knowledge of digital electronics and the Verilog Hardware description language. The lab will offer the student the opportunity to simulate and hardware analyze memory structures and compare bandwidth access for internal and external memory structures. The laboratory session requires a MAX10 DE10-Lite Development kit, Quartus Prime-Lite software and the Modelsim simulator.
Lab Manual: File:Intro to FPGA Memory Manual.docx
Lecture File:Intro Memory Workshop.pptx
New methods of higher level abstractions to describe digital electronics are gaining in popularity. RTL (Verilog and VHDL) remain the most common means to describe an FPGA, however C++ derivative languages such as OpenCL and HLS offer designers a means to describe computationally rich workloads that abstract away the low level details of memory interfaces, interchip connectivity and precise timing to increase designer productivity. This workshop describes this new programming paradigm and offer the students a new way to consider describing digital electronic functions. This workshop consists of a 1 hour lecture and 3 hour lab running Quartus FPGA development tools, Modelsim synthesis and the HLS compiler. Students should have a background in logic design and computer architecture.
Lab Manual: File:High Level Design Workshop Lab.pdf
Lecture File:Intro HighLevelDesign.pdf
The Acceleration Stack for Intel® Xeon® CPU with FPGAs is a robust collection of software, firmware, tools and hardware intended to make it easier to develop and deploy Intel FPGAs for workload optimization in data center and cloud environments. In this training, we will discuss and practice how software developers can write host code that can communicate with the FPGA accelerator transparently using the Open Programmable Acceleration Engine (OPAE) and walkthrough how FPGA and accelerator developers can build, test and integrate their Accelerator Functional Units (AFUs) into the FPGA. This workshop consists of 3 hours of lecture and demonstrations and 1 hour of hands-on lab work using Intel's virtual training machines.
Lab Manual: File:AccelStack Training LabInstructions.docx
Lecture File:AccelStack Seminar 1.1.pdf
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