Using DFI memory controllers with the Altera PHY Interface (AFI)

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Using DFI memory controllers with the Altera PHY Interface (AFI)

Using DFI memory controllers with the Altera PHY Interface (AFI)



This article describes the basic method and limitations for how one might interconnect a memory controller using a DDR PHY Interface (DFI) to an Altera PHY IP core which uses the Altera PHY Interface (AFI). Altera has never tested this and this is purely a proposal from analyzing both interface specifications. DFI is not officially suported by Altera. 

What is DFI?

The DDR PHY Interface (DFI) is a industry standard interface protocol that defines the connectivity between a DDR memory controller and a DDR PHY. The specification is managed by Denali Software Inc and allows for easy interchanging between DFI based PHY and memory controllers from different vendors, ASICs, etc


Whats is AFI?

The Altera PHY Interface (AFI) standardizes and simplifies the interface between controller and PHY for Altera’s DDR AltMemPHY and UniPHY IP based memory designs. It allows easy interchange of non Altera controller RTL with Altera's high-performance controllers by including the entire calibration logic (known as the sequencer) in the PHY.


Comparison of DFI and AFI

At a very basic level, AFI is a subset of DFI. Overall the interfaces are very similar however the DFI has some features that AFI does not support as listed in the following table:

AFI/DFI bridge proposal

In developing a bridge to convert DFI to AFI most signals should be able to be connected one to one on the supported sub-interface sections, with the exception of the write interface. These are listed as follows. (AlteMemPHY usually uses the ctl_<> signal name, UniPHY uses afi_<>. Care is required in setting the correct DFI parameters, as mentioned below.

Control Interface

dfi_address => ctl_addr/afi_addr

dfi_bank => ctl_ba/afi_ba

dfi_cas_n => ctl_casn/afi_cas_n

dfi_cke => ctl_cke/afi_cke

dfi_cs_n => ctl_csn/afi_cs_n

dfi_odt => ctl_odt/afi_odt

dfi_ras_n => ctl_rasn/afi_ras_n

dfi_reset_n => ctl_rstn/afi_rst_n

dfi_we_n => ctl_wen/afi_we_n

Write Interface

dfi_wrdata => ctl_wdata/afi_wdata

dfi_wrdata_en => see below

dfi_wrdata_mask => ctl_dm/afi_dm

Read Interface

dfi_rddata_en => ctl_doing_read/afi_rdata_en(_full)

dfi_rddata <= ctl_rdata/afi_rdata

dfi_rddata_valid <= ctl_rdata_valid/afi_rdata_valid

Status Interface

dfi_init_complete <= ctl_cal_success/afi_cal_success

dfi_dram_clk_disable => ctl_mem_clk_disable/afi_mem_clk_disable

Write Interface Functionality

The AFI write interface although similar to the DFI interface, it has an extra signal controlling the start of the DQS burst. Care needs to be taken to take the appropriate DFI information and generate this logic correctly. The following is a diagram showing two supported write modes on AFI, depending on whether a full rate or a half rate PHY is being used.

As we can see, they dqs_burst signal goes high (or partially high in the half rate case) one clock cycle before the wdata and wdata_valid is asserted inline with the wdata. Also, (not shown here) is the timing relationship between the write data being presented on AFI relative to the write command being issued on AFI. This is determined by another AFI signal ctl_wlat which provides the controller the calibrated write latency value. The controller must drive ctl_cs_n (for the write command) and then wait ctl_wlat ctl_clk cycles before driving clt_wdata_valid and ctl_wdata.

The DFI write specification is shown in the following diagram (Figure 7 from the DFI specification):

Once the write command is issued, wrdata_en is asserted tphy_wrlat cycles later, wdata is presented a further tphy_wrdata cycles after that.

There are plenty of options here to generate the required AFI logic depending on how the DFI controller is configured. The simplest might be doing the following:

  1. Set tphy_wrlat to ctl_wlat and tphy_wrdata to 1.
  2. Pass dfi_wrdata_en through a register and assign it to the AFI signal ctl_wdata_valid
  3. "OR" dfi_wdata_en and the registered version of it, and assign to ctl_dqs_burst (or just the MSB bit in the half rate case, the LSB will be equivalent to ctl_wdata_valid) 
  4. dfi_wrdata connects to ctl_wdata directly

Read Interface Functionality

The read interface signals more or less line up one to one however one must ensure that the correct DFI controller has the correct parameter settings. The following diagram shows the timing required for AFI interfaces. Note that AltMemPHY half rate IP uses 2 bits for rdata_en and rdata_valid, these bits should be drive the same. Also note that afi_rdata_en is called ctl_doign_read with AltMemPHY IP. This stays high for as many clock cycles as local side beats that are required, ie. local_size (see Altera's EMI handbook for more info).

DFI has the following timing on reads.

To align this with AFI, trddata_en must be set to zero so that dfi_rdata_en is aligned with the read command. For AltMemPHY designs the calibrated read latency is presented to the AFI interface on signal ctl_rdlat, however UniPHY does not provide this information. This shouldn't be important for most DFI controllers as rddata_valid is provided by the PHY and the controller should be just waiting for it, however if tphy_rdlat is required to be set correctly, most likely one would have to use AltMemPHY.


  1. DFI is not officially supported by Altera
  2. The proposed solution in this article has never been tested
  3. Altera recommends using UniPHY IP on all new designs with device support 

External Links

  1. Altera's External Memory Interface Solutions Center
  2. Altera's External Memory Interface Handbook
  3. DFI Specification


Key Words

AFI, DFI, external memory PHY interfaces, Denali , Altera PHY interface, DDR PHY interface 




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Last update:
‎06-26-2019 02:26 AM
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