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Using set_parameter for Quartus compile directives in VHDL and Verilog

Description: This forum article is dedicated to help users apply the the set_parameter qsf assignment in order to enable or disable certain portions of their RTL code. This article should help users looking for synthesis directives, compiler directives, or conditional compilation directives, or macros for use with Quartus standard and Quartus Pro. This article also helps address users writing RTL in VHDL which does not allow for things like `ifdef found in Verilog.

Example using Verilog

  • Quartus qsf file should contain the following:
set_parameter -name ADD_RTL 0
  • The RTL at the top level will look as follows:
generate
    if (ADD_RTL == 1) begin
        <Code to be included or not included depending upon ADD_RTL value in qsf file.>
  end
endgenerate

Example using VHDL

  • Quartus qsf file should contain the following:
set_parameter -name ADD_RTL 0
  • The RTL at the top level will look as follows:
test_code : if (ADD_RTL=1) generate
        <Code to be included or not included depending upon ADD_RTL value in qsf file.>
end generate test_code;

Using set_parameter hierarchically

  • The set_parameter qsf assignment can also be used hierarchically in Quartus Standard, but can only be used at the top level in Quartus Pro.
set_parameter -name ADD_RTL 0 -to level1_inst/level2_inst/counter_inst
    • In the above, an instance called counter_inst contains the same generate code as shown above.
    • In Quartus Pro, to pass a parameter hierarchically, the parameter must be defined at the top level and manually passed through hierarchy until reaching the intended level.
Version history
Revision #:
3 of 3
Last update:
‎07-28-2020 12:27 PM
Updated by: