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Description: This forum article is dedicated to help users apply the the set_parameter qsf assignment in order to enable or disable certain portions of their RTL code. This article should help users looking for synthesis directives, compiler directives, or conditional compilation directives, or macros for use with Quartus standard and Quartus Pro. This article also helps address users writing RTL in VHDL which does not allow for things like `ifdef found in Verilog.
Example using Verilog
set_parameter -name ADD_RTL 0
generate
if (ADD_RTL == 1) begin
<Code to be included or not included depending upon ADD_RTL value in qsf file.>
end
endgenerate
Example using VHDL
set_parameter -name ADD_RTL 0
test_code : if (ADD_RTL=1) generate
<Code to be included or not included depending upon ADD_RTL value in qsf file.>
end generate test_code;
Using set_parameter hierarchically
set_parameter -name ADD_RTL 0 -to level1_inst/level2_inst/counter_inst
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