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What steps can I follow to ensure I don’t have transceiver calibration problems?

What steps can I follow to ensure I don’t have Intel® Cyclone® 10 GX, Intel® Arria® 10, or Intel® Stratix® 10 L/H-Tile transceiver calibration problems?

 

Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 L/H-Tile transceiver PHYs and TX PLLs must be calibrated before use.

 

There are two types of calibration for Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 L/H-Tile transceiver PHYs and TX PLLs. Power-up calibration, and user recalibration.

 

  • Power-up calibration takes place automatically “during” FPGA configuration.
  • User recalibration takes place when you request it on the PHY or TX PLL Avalon Memory Mapped interface bus.
  • Resetting the PHY or TX PLL does not recalibrate them

 

Intel Cyclone 10 GX and Intel Arria 10 devices

 

The requirements for your Intel Quartus Prime project are:

  • The Intel® Quartus® Prime Configuration Clock (Device Initialization Clock) source must use the CLK_USR option.
  • Ensure each transceiver TX and RX channel in your Intel Quartus Prime project design has a corresponding “XCVR_VCCR_VCCT_VOLTAGE" QSF assignment that matches the voltage on your PCB.
  • Ensure the VCCR_GXB and VCCT_GXB supply voltage setting of all PHYs in your design match the voltage on the PCB and the QSF assignment.
  • The QSF to PCB VCCR_GXB and VCCT_GXB voltage mapping is detailed here.

    https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/hsio/2...

 

The requirements for successful power-up calibration are:

  • The CLK_USR signal must be toggling at the correct frequency “before” FPGA configuration begins.
  • The reference clock feeding the TX PLL and PHY IP’s in your design must be running at the correct frequencies “before” FPGA configuration begins.

 

When should I perform a user recalibration?:

  • If the power-up calibration conditions are not met, you must perform a user recalibration.
  • In general, if you dynamically reconfigure the TX PLL, or PHY to a different data rate or reference clock you must perform a user recalibration.
  • Some Intel FPGA IP like HDMI or DisplayPort recalibrate automatically after a resolution change.

 

The requirements for successful user recalibration are:

  • The CLK_USR signal must be toggling at the correct frequency.
  • The reference clock signal feeding the TX PLL or PHY IP you are recalibrating must be running at the correct frequency.

 

Other Considerations:

  • Intel Arria 10 and Intel Cyclone 10 GX devices have a single shared PreCISE calibration engine per transceiver column.
  • During power-up calibration, PCI Express* transceivers are calibrated first, followed sequentially starting from the bottom of the transceiver column to the top.
  • If you need to perform a user recalibration on multiple TX PLL or PHY IP in your design, you must perform them sequentially.

 

Using the Transceiver Toolkit to recalibrate your transceivers.

 

You can refer to the Intel Cyclone 10 GX Transceiver PHY User Guide or Intel Arria 10 Transceiver PHY User Guide for further details and recalibration examples.

 

Intel Stratix 10 L- & H-Tile Devices

 

The requirements for your Intel Quartus Prime project are:

 

The requirements for successful power-up calibration are:

  • The OSC_CLK_1 signal must be toggling at the correct frequency “before” FPGA configuration begins
  • The reference clock feeding the TX PLL and PHY IP’s in your design must be running at the correct frequencies “before” FPGA configuration begins.

 

When should I perform a user recalibration?:

  • If the power-up calibration conditions are not met, you must perform a user recalibration.
  • In general, if you dynamically reconfigure the TX PLL, or PHY to a different data rate or reference clock you must perform a user recalibration.
  • Some Intel FPGA IP like HDMI or DisplayPort recalibrate automatically after a resolution change.

 

The requirements for successful user recalibration are:

  • The OSC_CLK_1 signal must be toggling at the correct frequency.
  • The reference clock signal feeding the TX PLL or PHY IP you are recalibrating must be running at the correct frequency.

 

Other Considerations:

  • Intel Stratix 10 L & H-Tile devices have a dedicated PreCISE calibration engine per duplex channel or TX PLL
  • If you need to perform a user recalibration on multiple TX PLL or PHY IP in your design, you can do this in parallel.

 

Using the Transceiver Toolkit to recalibrate your transceivers.

 

You can refer to the Intel Stratix 10 L/H-Tile Transceiver PHY IP User Guide for further details and recalibration examples.

 

2021-04-28

James Murray

 

Notices & Disclaimers

 

Intel technologies may require enabled hardware, software or service activation.

No product or component can be absolutely secure.

Your costs and results may vary.

© Intel Corporation.  Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus

and Stratix, and other Intel marks are trademarks of Intel Corporation or its subsidiaries.  Other names and brands may be claimed as the property of others.

The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications.  Current characterized errata are available on request.​

 

 

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Last update:
‎04-28-2021 06:43 AM
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