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fatal error: 'exception_handler.hpp' file not found

ruma
Beginner
927 Views

Hello everyone!!! Can you help me please? I have a error when i want to compiler and execute samples one api.

-------------------------------------------------------------------------------------------------------

- fatal error: 'exception_handler.hpp' file not found
#include "exception_handler.hpp"
^~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
src/CMakeFiles/loop_unroll.fpga_sim.dir/build.make:62: recipe for target 'src/CMakeFiles/loop_unroll.fpga_sim.dir/loop_unroll.cpp.o' failed
make[3]: *** [src/CMakeFiles/loop_unroll.fpga_sim.dir/loop_unroll.cpp.o] Error 1
CMakeFiles/Makefile2:195: recipe for target 'src/CMakeFiles/loop_unroll.fpga_sim.dir/all' failed
make[2]: *** [src/CMakeFiles/loop_unroll.fpga_sim.dir/all] Error 2
CMakeFiles/Makefile2:303: recipe for target 'src/CMakeFiles/fpga_sim.dir/rule' failed
make[1]: *** [src/CMakeFiles/fpga_sim.dir/rule] Error 2
Makefile:196: recipe for target 'fpga_sim' failed
make: *** [fpga_sim] Error 2

--------------------------------------------------------------------------------------------------------

 

I think is a new version for this year 2023, but I don`t know!!! 

 

Thansks for readme.

 

Best regards!!!!

 

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1 Solution
AthiraM_Intel
Moderator
897 Views

Hi,

 

Thank you for posting in Intel Communities.

 

Could you please let us know which DevCloud you are using? Is it DevCloud for oneAPI/ DevCloud for Edge/ FPGA DevCloud ?

 

Also share the the sample you are trying and the exact steps you followed?

 

 

Thanks

 

View solution in original post

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4 Replies
AthiraM_Intel
Moderator
898 Views

Hi,

 

Thank you for posting in Intel Communities.

 

Could you please let us know which DevCloud you are using? Is it DevCloud for oneAPI/ DevCloud for Edge/ FPGA DevCloud ?

 

Also share the the sample you are trying and the exact steps you followed?

 

 

Thanks

 

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ruma
Beginner
886 Views

Hello

 

It is Devcloud for onepi.

 

This is the example:

 

//==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>
#include <iomanip>
#include <iostream>
#include <string>
#include <vector>

#include "exception_handler.hpp"

using namespace sycl;

// Forward declare the kernel name in the global scope.
// This FPGA best practice reduces name mangling in the optimization reports.
template <int unroll_factor> class VAdd;

// This function instantiates the vector add kernel, which contains
// a loop that adds up the two summand arrays and stores the result
// into sum. This loop will be unrolled by the specified unroll_factor.
template <int unroll_factor>
void VecAdd(const std::vector<float> &summands1,
const std::vector<float> &summands2, std::vector<float> &sum,
size_t array_size) {


#if defined(FPGA_EMULATOR)
ext::intel::fpga_emulator_selector device_selector;
#elif defined(FPGA_SIMULATOR)
ext::intel::fpga_simulator_selector device_selector;
#else
ext::intel::fpga_selector device_selector;
#endif

try {
queue q(device_selector, fpga_tools::exception_handler,
property::queue::enable_profiling{});

buffer buffer_summands1(summands1);
buffer buffer_summands2(summands2);
buffer buffer_sum(sum);

event e = q.submit([&](handler &h) {
accessor acc_summands1(buffer_summands1, h, read_only);
accessor acc_summands2(buffer_summands2, h, read_only);
accessor acc_sum(buffer_sum, h, write_only, no_init);

h.single_task<VAdd<unroll_factor>>([=]()
[[intel::kernel_args_restrict]] {
// Unroll the loop fully or partially, depending on unroll_factor
#pragma unroll unroll_factor
for (size_t i = 0; i < array_size; i++) {
acc_sum[i] = acc_summands1[i] + acc_summands2[i];
}
});
});

double start = e.get_profiling_info<info::event_profiling::command_start>();
double end = e.get_profiling_info<info::event_profiling::command_end>();
// convert from nanoseconds to ms
double kernel_time = (double)(end - start) * 1e-6;

std::cout << "unroll_factor " << unroll_factor
<< " kernel time : " << kernel_time << " ms\n";
std::cout << "Throughput for kernel with unroll_factor " << unroll_factor
<< ": ";
std::cout << std::fixed << std::setprecision(3)
#if defined(FPGA_SIMULATOR)
<< ((double)array_size / kernel_time) / 1e3f << " MFlops\n";
#else
<< ((double)array_size / kernel_time) / 1e6f << " GFlops\n";
#endif

} catch (sycl::exception const &e) {
// Catches exceptions in the host code
std::cerr << "Caught a SYCL host exception:\n" << e.what() << "\n";

// Most likely the runtime couldn't find FPGA hardware!
if (e.code().value() == CL_DEVICE_NOT_FOUND) {
std::cerr << "If you are targeting an FPGA, please ensure that your "
"system has a correctly configured FPGA board.\n";
std::cerr << "Run sys_check in the oneAPI root directory to verify.\n";
std::cerr << "If you are targeting the FPGA emulator, compile with "
"-DFPGA_EMULATOR.\n";
}
std::terminate();
}
}

int main(int argc, char *argv[]) {
#if defined(FPGA_SIMULATOR)
size_t array_size = 1 << 10;
#else
size_t array_size = 1 << 26;
#endif

if (argc > 1) {
std::string option(argv[1]);
if (option == "-h" || option == "--help") {
std::cout << "Usage: \n<executable> <data size>\n\nFAILED\n";
return 1;
} else {
array_size = std::stoi(option);
}
}

std::vector<float> summands1(array_size);
std::vector<float> summands2(array_size);

std::vector<float> sum_unrollx1(array_size);
std::vector<float> sum_unrollx2(array_size);
std::vector<float> sum_unrollx4(array_size);
std::vector<float> sum_unrollx8(array_size);
std::vector<float> sum_unrollx16(array_size);

// Initialize the two summand arrays (arrays to be added to each other) to
// 1:N and N:1, so that the sum of all elements is N + 1
for (size_t i = 0; i < array_size; i++) {
summands1[i] = static_cast<float>(i + 1);
summands2[i] = static_cast<float>(array_size - i);
}

std::cout << "Input Array Size: " << array_size << "\n";

// Instantiate VecAdd kernel with different unroll factors: 1, 2, 4, 8, 16
// The VecAdd kernel contains a loop that adds up the two summand arrays.
// This loop will be unrolled by the specified unroll factor.
// The sum array is expected to be identical, regardless of the unroll factor.
VecAdd<1>(summands1, summands2, sum_unrollx1, array_size);
VecAdd<2>(summands1, summands2, sum_unrollx2, array_size);
VecAdd<4>(summands1, summands2, sum_unrollx4, array_size);
VecAdd<8>(summands1, summands2, sum_unrollx8, array_size);
VecAdd<16>(summands1, summands2, sum_unrollx16, array_size);

// Verify that the output data is the same for every unroll factor
for (size_t i = 0; i < array_size; i++) {
if (sum_unrollx1[i] != summands1[i] + summands2[i] ||
sum_unrollx1[i] != sum_unrollx2[i] ||
sum_unrollx1[i] != sum_unrollx4[i] ||
sum_unrollx1[i] != sum_unrollx8[i] ||
sum_unrollx1[i] != sum_unrollx16[i]) {
std::cout << "FAILED: The results are incorrect\n";
return 1;
}
}
std::cout << "PASSED: The results are correct\n";
return 0;
}

 

And the steps, I follow:

1.- ssh devcloud

2.-  qsub -I -l walltime=24:00:00 -l nodes=1:arria10:ppn=2 -d .

3.-  cd loop_unroll/build/

4.- cmake ..

5.- make fpga_emu

 

12@s001-n085:~/loop_unroll/build$ make fpga_emu
[ 50%] Building CXX object src/CMakeFiles/loop_unroll.fpga_emu.dir/loop_unroll.cpp.o
/home/u114512/loop_unroll/src/loop_unroll.cpp:13:10: fatal error: 'exception_handler.hpp' file not found
#include "exception_handler.hpp"
^~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
src/CMakeFiles/loop_unroll.fpga_emu.dir/build.make:62: recipe for target 'src/CMakeFiles/loop_unroll.fpga_emu.dir/loop_unroll.cpp.o' failed
make[3]: *** [src/CMakeFiles/loop_unroll.fpga_emu.dir/loop_unroll.cpp.o] Error 1
CMakeFiles/Makefile2:158: recipe for target 'src/CMakeFiles/loop_unroll.fpga_emu.dir/all' failed
make[2]: *** [src/CMakeFiles/loop_unroll.fpga_emu.dir/all] Error 2
CMakeFiles/Makefile2:239: recipe for target 'src/CMakeFiles/fpga_emu.dir/rule' failed
make[1]: *** [src/CMakeFiles/fpga_emu.dir/rule] Error 2
Makefile:170: recipe for target 'fpga_emu' failed
make: *** [fpga_emu] Error 2

 

Thanks for you help.

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ruma
Beginner
872 Views

Hello AthiraM_Intel.

 

In this moment, Right now. I follow this steps and the example compiled correctly.

 

And the steps, I follow:

1.- ssh devcloud

2.-  qsub -I -l walltime=24:00:00 -l nodes=1:arria10:ppn=2 -d .

3.-  cd loop_unroll/build/

4.- cmake ..

5.- make fpga_emu

 

Thanks for all. Best regards.-

 

Rubén

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AthiraM_Intel
Moderator
854 Views

Hi,


Glad to know that your issue is resolved. Thanks for sharing the solution with us. If you need any additional information, please post a new question as this thread will no longer be monitored by Intel.



Thanks


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