Install OpenVINO with FPGA

[Kamal_Devanga]

Hello,

I have a couple of questions regarding the installation of OpenVINO with FPGA support. The installation instructions on this link https://software.intel.com/en-us/articles/OpenVINO-Install-Linux-FPGA direct us to the following link https://software.intel.com/en-us/articles/OpenVINO-Install-Linux-FPGA#setupA10GX, but I am confused as to how to set up the correct configuration.

Up to which point shall we follow instructions on the second link? It seems that according to the section "Initializing the Intel Arria 10 GX FPGA Development Kit for use with OpenCL" of the second link, we need to install FPGA SDK for OpenCL so that we can obtain files max5_150.pof, top.sof, and boardtest.aocx, with which we program the FPGA. After that, the second link proceeds to run the command "aocl install" using the FPGA SDK for OpenCL.

On the other hand, the first link says to invoke aocl from the FPGA RTE for OpenCL installed with OpenVINO. From what I have seen, the RTE installed with OpenVINO does not come with the three files required for the above step, so I feel that we end up with both SDK and RTE.

Could someone help me figure out the exact steps?

Thanks

[Mark_L_Intel1]

Hi Kumazawa San,

Yes, the second link is correct, there is a link in the second link that point to AN807, this should be the place where you start with Arris 10.

The instruction also assumes using CentOS instead of Ubuntu, which system are you using, hardware and OS info?

Mark

[Daiki_K_Intel]

Hi Mark:

Thanks for your reply. I will give it another shot by following the link you provided.

I am using Ubuntu 16.04 with Arria 10 GX. Will there be any difference in the case of Ubuntu?

Daiki

[Mark_L_Intel1]

Yes, in general, the environment will be different.

I have send you an invitation to internal group, let's discuss there.

Mark

[Gdeep]

Can you help me for  the 'Program the Intel® Arria® 10 GX FPGA Development Kit'

I am installing the openvino with Linux FPGA support, I followed all the steps (which given on Intel website) to program the FPGA I successfully executed  'quartus_pgm -c 1 -m JTAG -o "p;top.sof' this file but the problem is here:-

When i ran "quartus_pgm -c 1 -m JTAG -o "p;max5_150.pof@2" i is throwing the error which is mentioned below:-

Device index 1 must be less than device index of physical JTAG chain. check board or choose legal device index '

Can anybody help me to sort out this error

[David_D_Intel]

Hi Gagan,

Would you mind opening a separate thread for this topic?

First, make sure that the USB cable is firmly plugged in.  It can slip out very easily from the micro-usb side that connects to the FPGA.

After that, run 'jtagconfig'.  This will return a list of 2 devices if it works, or a failure message about "No JTAG hardware available".  It's a good idea to always check that jtagconfig detects the cable, before using quartus_pgm or 'aocl flash'.

Also, after confirming the USB cable is detected, and before running quartus_pgm or 'aocl flash', always slow down the jtagclock as listed in the documentation: 

jtagconfig --setparam 1 JtagClock 6M

If jtagconfig reports that it detects devices, and you slow down the clock, quartus_pgm should work. 

[Gdeep]

Dear David 

I have created a new thread, the link is :-  https://software.intel.com/node/801652

I have done whatever you said but am not able to detect MAX 5, please ones go through with the link which I mentioned above where I have given full detail about my problem