Stratix 10 GSRD Development Issues

[RLambdin92]

Currently working with the GSRD Users Guide from the Rocketboards archives (https://altera-fpga.github.io/rel-24.3/embedded-designs/stratix-10/sx/soc/gsrd/ug-gsrd-s10sx-soc/#partial-reconfiguration_1). Have been attempting to try and better understand the Partial Reconfiguration portion of the design and have made some attempts at trying to modify the design and rebuild from there.

I've walked through the process fully to get the initial build fully developed and working. I then attempted to edit the top level of the design by disconnecting the user LEDs from the Qsys Top and hard coding their values. I went through the entire process again and replaced the ghrd_s10_top.sv with the LED changes before running "make all". Going through the entire rebuild process and the Yocto rebuild, I produced a JIC and SDCard Image which i loaded the same way as the working build. But when I attempt the "dtbt" device tree to apply either Persona, the command gets stuck and pushes a "Stratix10 SoC FPGA manager soc:firmware:svc:fpga-mgr: timeout waiting for svc layer buffers".

Looking for any assistance on the process of applying changes to the design and rebuilding this PR design. Thanks for any assistance

p.s. Will be out of office till Monday but posting now as the error it hitting in case theres some assistance before the Holiday break.

[Wan_Intel]

Hi RLambdin92,

Thank you for reaching out to OpenVINO™ community!

For your information, we received an update from the relevant team as follows:

FPGA products are no longer under Intel®, they are under a separate company, Altera®. Therefore, we request you to post your queries in Altera® Community.

Regards,

Wan

[Wan_Intel]

Hi RLambdin92,

Thank you for your question.

If you have additional information from Intel, please submit a new thread as this thread will no longer be monitored.

Regards,

Wan