How can I establish Ethernet Communication with my Altera DE2-115 FPGA development board for FPGA-In-Loop Wizard in MATLAB to run?

[RVerm5]

Hi, I am trying to use FPGA-In-Loop wizard to verify and run my Verilog Code on Altera DE2-115 Development Board. FIL wizard isn't giving me an option for JTAG communication with the FPGA board, so I am left with Ethernet as the only mode of communication. I have tried following the steps mentioned in https://in.mathworks.com/help/hdlverifier/examples/verify-hdl-implementation-of-pid-controller-using-fpga-in-the-loop.html, but I am unable to establish the computer-board connection in Windows 7. Please suggest what errors I might be making or if there is any other way of establishing the connection. One observation I could make was that I was unable to locate any "connection icon to your FPGA development board" as mentioned in the above link. Please help.

[YuanLi_S_Intel]

Hi,

I gone through the link that you have provided. Please note that we did not tested the examples provided from another Vendor.

As a primary debugging check, is it possible to get the link from FPGA that means ping test is passing.

And please note that the development kit provides JTAG connectivity 

Page no:10

ftp://ftp.altera.com/up/pub/Altera_Material/Boards/DE2-115/DE2_115_User_Manual.pdf

Hope it helps.

Thank You.

Regards,

YL