Intel® FPGA Software Installation & Licensing
Installation and Licensing that’s includes Intel Quartus® Prime software, ModelSim* - Intel FPGA Edition software, Nios® II Embedded Design Suite on Windows or Linux operating systems.

#287035 problem


when i use "abs" Quartus has Errors

Error (287035): Text Design File must contain a Subdesign and Logic Section

Error (12006): Node instance "add_sub_15" instantiates undefined entity "add_sub_fpc"

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 2 errors, 1 warning

Error: Peak virtual memory: 4715 megabytes

Error: Processing ended: Sun Dec 08 12:25:24 2019

Error: Elapsed time: 00:00:36

Error: Total CPU time (on all processors): 00:00:28

Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning


like this


     elsif(cal_result < 0 and cal_result > -10) then

      num1_1 <= 20;

      num1_2 <= 20;

      num1_3 <= 20;

      num1_4 <= 20;

      num1_5 <= 18;

      num1_6 <= (abs(cal_result) mod 10);


this is my code

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In a Text Design File (.tdf), you did not use a Subdesign Section or Logic Section. A TDF must contain both a Subdesign Section and a Logic Section. You cannot declare these sections in a separate AHDL Include File (.inc) and then try to include them in a TDF using an Include Statement.


You have to make sure that the TDF contains both a Subdesign Section and a Logic Section. Do not declare the Subdesign Section or Logic Section in a separate AHDL Include File.




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